bottom up synthesis with parameterized design

Discussion in 'VHDL' started by Marco Lazar, Apr 22, 2004.

  1. Marco Lazar

    Marco Lazar Guest

    Hi,

    i have a question on how to do bottom up synthesis (elaboration)
    in design compiler with a highly parameterized design. I am
    aware of the -parameter switch and it works great on the designs
    at the bottom of the hierarchy but as soon as i try to elaborate
    modules at one level higher up in the hierarchy, the tool has problems
    finding and using the previously synthesized blocks. The tool spits
    out warnings and errors complaining that it can't link the design.

    So i was wondering if anybody out there has a sample design compiler
    script which does a bottom up synthesis on a parameterized design.


    Thanks in advance !!
    Marco
    Marco Lazar, Apr 22, 2004
    #1
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