building hierarcy error

[vivo_m]

hello,

i've buit two components and ensured that they are doing their functionality well..
now i'm trying to connect them together in a new vhdl..
i already set the ports but i've nothing to write in the architecture body
i got this error message ( Formal port "clk" has OPEN or no actual associated with it.)
this msg is repeated for every i/p port as happened with the clk

any idea how to overcome this..