building hierarcy error

Discussion in 'VHDL' started by vivo_m, Feb 24, 2012.

  1. vivo_m

    vivo_m

    Joined:
    Feb 23, 2012
    Messages:
    3
    hello,

    i've buit two components and ensured that they are doing their functionality well..
    now i'm trying to connect them together in a new vhdl..
    i already set the ports but i've nothing to write in the architecture body
    i got this error message ( Formal port "clk" has OPEN or no actual associated with it.)
    this msg is repeated for every i/p port as happened with the clk

    any idea how to overcome this..
    vivo_m, Feb 24, 2012
    #1
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