Clock sampling with unisim FDCPE (virtex5)

Discussion in 'VHDL' started by eko, Sep 17, 2008.

  1. eko

    eko

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    Hi everybody,

    following an application note from Xilinx I implemented a quad-port ram. Now when I simulated this with modelsim I recognized that the FDCPEs do not propagate what they should. Basically those are used to sample the (inverted) normal clock by a clock with doubled speed.
    Relevant code snippets:
    Code (Text):


    ...

    COMPONENT FDCPE
       GENERIC (
          INIT : bit
       );
       PORT (
          C   : IN     std_ulogic;
          CE  : IN     std_ulogic;
          CLR : IN     std_ulogic;
          D   : IN     std_ulogic;
          PRE : IN     std_ulogic;
          Q   : OUT    std_ulogic
       );
       END COMPONENT;

       -- Optional embedded configurations
       -- pragma synthesis_off
       FOR ALL : FDCPE USE ENTITY unisim.FDCPE;
       -- pragma synthesis_on

    BEGIN

       low <= '0';
       high <= '1';

    i_clkbd_lacff : FDCPE
          GENERIC MAP (
             INIT => '0'
          )
          PORT MAP (
             Q   => clkbd_lac,
             C   => clkbdx2,
             CE  => high,
             CLR => rst,
             D   => notclkbd,
             PRE => low
          );

    ...

     
    Whereby clkbdx2 is twice clock clkbd, doubled with an DCM.
    notclkbd is simply the inverted clkbd.
    rst is reset (checked already - is active as it should be).
    Both clocks are routed via an bufg after the dcm.

    clkbd_lac (what is the output of the FDCPE) is set to one after the reset and stays high all the time. Although I see the input toggeling.

    All i/o signals are std_logic.

    Simulating with 100fs time resolution.

    Is there any known reason why this could be?

    Thanx,

    wondering,

    e.
     
    eko, Sep 17, 2008
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  2. eko

    eko

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    Well, I now solved this by adding an "after 1 ps" to the clock inverter. Although thats all fine with me, I still wonder why Modelsim could not take it without that. I thought the inverter should have told it that there is some delay, that makes a sampling of the clock by another clock possible...
     
    eko, Sep 17, 2008
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