compteur VHDL

Discussion in 'VHDL' started by Martial DOERPER, Mar 8, 2005.

  1. Bonjour, j'ai réaliser un compteur VHDL qui compte de 0 a 7 (cycle
    d'horloge).
    Celui ci possede une sortie qui est censée passé a '1' uniquement lorsque le
    compteur vaut 7 (soit les 3bits a '1').
    Or au passage de 3 à 4 par exemple et de 5 à 6 on observe une impulsion sur
    la sortie.
    Comment y remédier?
    Merci de votre aide
    Fichier détaillé : http://martial.doerper.free.fr/compteur.doc
    Martial
     
    Martial DOERPER, Mar 8, 2005
    #1
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  2. Martial DOERPER

    jandc Guest

    > Bonjour, j'ai réaliser un compteur VHDL qui compte de 0 a 7 (cycle
    > d'horloge).
    > Celui ci possede une sortie qui est censée passé a '1' uniquement lorsque le
    > compteur vaut 7 (soit les 3bits a '1').
    > Or au passage de 3 à 4 par exemple et de 5 à 6 on observe une impulsion sur
    > la sortie.
    > Comment y remédier?
    > Merci de votre aide
    > Fichier détaillé : http://martial.doerper.free.fr/compteur.doc
    > Martial


    In this newsgroup it's custom to correspond in english, as you might
    have noticed. I don't care if it's bad english as long as you at least try.

    Now for your problem: are those wavetraces from a vhdl simulation,
    netlist simulation or real live? Anyway what environment are you using?

    Jan
     
    jandc, Mar 9, 2005
    #2
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  3. Martial DOERPER

    Alan Fitch Guest

    "Martial DOERPER" <> wrote in message
    news:422e201a$0$9518$...
    > Bonjour, j'ai réaliser un compteur VHDL qui compte de 0 a 7 (cycle
    > d'horloge).
    > Celui ci possede une sortie qui est censée passé a '1' uniquement

    lorsque le
    > compteur vaut 7 (soit les 3bits a '1').
    > Or au passage de 3 à 4 par exemple et de 5 à 6 on observe une

    impulsion sur
    > la sortie.
    > Comment y remédier?
    > Merci de votre aide


    If you have put combinational decode logic on the output of the
    counter,
    then you *will* see "glitches" (changes in value as the combinational
    logic
    propagates values to its output).

    You can synchronise your decode with another register, but then your
    signal will
    appear one clock later.

    If that is a problem, you could decode the number 6 (one clock cycle
    earlier) and
    then register the decode output so that the pulse occurs at the
    correct time, e.g.

    architecture
    signal count : unsigned(2 downto 0);
    begin

    process(clock, reset)

    begin
    if reset = '1' then
    count <= (others => '0');
    elsif rising_edge(clock) then
    output <= '0';
    count <= count + 1;
    if (count = "110") then
    output <= '1'; -- will be register
    end if;
    end if;
    end process;

    end;



    regards
    Alan
    --
    Alan Fitch
    Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
    Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
    1AW, UK
    Tel: +44 (0)1425 471223 mail:

    Fax: +44 (0)1425 471573 Web:
    http://www.doulos.com

    The contents of this message may contain personal views which are not
    the
    views of Doulos Ltd., unless specifically stated.
     
    Alan Fitch, Mar 9, 2005
    #3
  4. Martial DOERPER

    bxbxb3 Guest

    While simulating your code, I didn't find any glitches! I used ModelSIM PE
    5.7e and made two corrections in your code, which was deleting the word
    "entity" in "end entity compt8" line and deleting architecture in the last
    line and replacing it with "comport".
     
    bxbxb3, Mar 11, 2005
    #4
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