Conditional "FOR..GENERATE" generic construct?

Discussion in 'VHDL' started by Pasacco, May 18, 2007.

  1. Pasacco

    Pasacco Guest

    Hi

    I have problem with using "FOR...GENERATE" of generic component.

    My goal is to use "FOR...GENERATE" construct,
    in order to instantiate different modules,
    depending on condition.

    "Exercise1" below works fine.

    "Exercise2"-style of construct below does not work.

    Question is that
    Does VHDL support "Exercise2" style of construct?

    If yes, could anyone point out where I can find some examples?

    ----------------------------------------------------------------
    -- Exercise1 : Homogeneous modules
    ---------------------------------------------------------------
    -- MAX : maximum number of instantiated components

    CTRL : for i in 0 to MAX-1 generate
    Module : Logic_Module
    port map(
    CLK => CLK, -- clock
    RST => RST, -- reset
    IN1_i => IN1(i), -- input port
    OUT1_o => OUT1(i) ); -- output port
    end generate CTRL;
    ---------------------------------------------------------------

    ----------------------------------------------------------------
    -- Exercise2: Trying to optimize heterogenous modules
    -- Temp : integer type signal
    ---------------------------------------------------------------
    CTRL : for i in 0 to MAX-1 generate

    if Temp(i) = 0 then --- In this condition, instantiate Logic_ModuleA

    ModuleA : Logic_ModuleA
    port map(
    CLK => CLK,
    RST => RST,
    IN1_i => IN1(i),
    OUT1_o => OUT1(i) );

    else --- In this condition, instantiate Logic_ModuleB

    ModuleB : Logic_ModuleB
    port map(
    CLK => CLK,
    RST => RST,
    IN1_i => IN1(i),
    OUT1_o => OUT1(i) );

    end generate CTRL;
    ---------------------------------------------------------------
     
    Pasacco, May 18, 2007
    #1
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  2. On 18 May 2007 08:31:36 -0700,
    Pasacco <> wrote:

    >----------------------------------------------------------------
    >-- Exercise2: Trying to optimize heterogenous modules
    >-- Temp : integer type signal
    >---------------------------------------------------------------
    >CTRL : for i in 0 to MAX-1 generate
    >
    >if Temp(i) = 0 then --- In this condition, instantiate Logic_ModuleA


    You need another nested GENERATE construct for this "if".

    MOD_CHOICE_A: if Temp(i) = 0 generate
    > ModuleA : Logic_ModuleA
    > port map(
    > CLK => CLK,
    > RST => RST,
    > IN1_i => IN1(i),
    > OUT1_o => OUT1(i) );

    end generate; -- MOD_CHOICE

    >else --- In this condition, instantiate Logic_ModuleB


    Sadly, you cannot have ELSE on IF...GENERATE, so you must do...

    MOD_CHOICE_B: if Temp(i) /= 0 generate
    > ModuleB : Logic_ModuleB

    ....

    Note, also, that Temp() must be a constant of some kind -
    a generic, or a constant. No signals, no variables.

    Hope this helps
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, May 18, 2007
    #2
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  3. In news: timestamped Fri, 18
    May 2007 16:37:35 +0100, Jonathan Bromley
    <> posted:
    "[..]

    Sadly, you cannot have ELSE on IF...GENERATE, [..]

    [..]"

    ELSE is allowed for GENERATE in Draft IEEE P1076/D3.4, April 26, 2007
    but I am not aware of a tool which supports this.
     
    Colin Paul Gloster, May 18, 2007
    #3
  4. Pasacco

    Pasacco Guest

    Synthesizer synthesizes as expected.
    While functionality is under test,
    Your remark was very helpful.
    Thank you.
     
    Pasacco, May 18, 2007
    #4
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