Creating delay in divider

Discussion in 'VHDL' started by THurkmans, Nov 4, 2009.

  1. THurkmans

    THurkmans Guest

    Hello,

    I have a design in which I have a 1/x operation, which cannot be
    optimized away. I'm using the fixed-point library of the new vhdl
    standard, which supplies me with a reciprocal function.

    Synthesizing such a design in synplify is giving me an sdiv block, and
    a very large delay (probably due to the fact that it operates in one
    clock cycle).

    How can I modify my design such that I can still use the reciprocal
    function of the fixed point library, but have a delay of multiple
    clock cycles? Or do I have to build a dedicated divider?

    Greetings,
    Tim
    THurkmans, Nov 4, 2009
    #1
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  2. THurkmans

    KJ Guest

    On Nov 4, 10:22 am, THurkmans <> wrote:

    > How can I modify my design such that I can still use the reciprocal
    > function of the fixed point library, but have a delay of multiple
    > clock cycles? Or do I have to build a dedicated divider?
    >


    Google for lpm_divide. It's a divider that operates on multiple clock
    cycles.

    KJ
    KJ, Nov 4, 2009
    #2
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