Dumping real signals in VCD

Discussion in 'VHDL' started by Sajan, Sep 19, 2003.

  1. Sajan

    Sajan Guest

    Hi
    I am dumping signals which are declared as integer and real.
    But i cant find these signals in the dump file.
    Can anyone tell me why this happens and how to over this.
    Regards,
    Sajan.
     
    Sajan, Sep 19, 2003
    #1
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  2. Sajan

    Sajan Guest

    Well i forgot to mention that I am using Modelsim to do this.


    (Sajan) wrote in message news:<>...
    > Hi
    > I am dumping signals which are declared as integer and real.
    > But i cant find these signals in the dump file.
    > Can anyone tell me why this happens and how to over this.
    > Regards,
    > Sajan.
     
    Sajan, Sep 19, 2003
    #2
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  3. Sajan,
    Not sure if you are talking about VHDL or Verilog, either way
    Modelsim can
    probe real signals/variables in its waveform. When you say "VCD" how
    do you create your VCD? That may be where the problem is, can you show
    us how you dump VCD?

    Ajeetha
    http://www.noveldv.com

    (Sajan) wrote in message news:<>...
    > Well i forgot to mention that I am using Modelsim to do this.
    >
    >
    > (Sajan) wrote in message news:<>...
    > > Hi
    > > I am dumping signals which are declared as integer and real.
    > > But i cant find these signals in the dump file.
    > > Can anyone tell me why this happens and how to over this.
    > > Regards,
    > > Sajan.
     
    Ajeetha Kumari, Sep 20, 2003
    #3
  4. Sajan

    Sajan Guest

    Hi
    I am using VHDL.
    I use the following commands in the modelsim commandline
    interface to dump the signals.

    vcd file dump.vcd
    vcd add /top/* /*I assume this means dump all signals */

    I can see real signals in the wlf format of Modelsim but not in the VCD format
    in which am trying to dump the signals.

    Thanks and Regards,
    Sajan.


    (Ajeetha Kumari) wrote in message news:<>...
    > Sajan,
    > Not sure if you are talking about VHDL or Verilog, either way
    > Modelsim can
    > probe real signals/variables in its waveform. When you say "VCD" how
    > do you create your VCD? That may be where the problem is, can you show
    > us how you dump VCD?
    >
    > Ajeetha
    > http://www.noveldv.com
    >
    > (Sajan) wrote in message news:<>...
    > > Well i forgot to mention that I am using Modelsim to do this.
    > >
    > >
    > > (Sajan) wrote in message news:<>...
    > > > Hi
    > > > I am dumping signals which are declared as integer and real.
    > > > But i cant find these signals in the dump file.
    > > > Can anyone tell me why this happens and how to over this.
    > > > Regards,
    > > > Sajan.
     
    Sajan, Sep 22, 2003
    #4
  5. Sajan,
    You seem to be correct, some how the "vcd add" misses out real
    signals in VHDL. Initially I tried a Verilog example, that worked fine
    with vcd add command. Looks like only the VHDL part of it has some
    issue.

    Sorry, couldn't be of much help, perhaps contact Modelsim support? Why
    do you prefer VCD against WLF?

    > vcd add /top/* /*I assume this means dump all signals */
    >


    This adds all signals in top instance, use with -r if you want the
    whole hierarchy (I guess you know that already).

    Ajeetha
    http://www.noveldv.com

    (Sajan) wrote in message news:<>...
    > Hi
    > I am using VHDL.
    > I use the following commands in the modelsim commandline
    > interface to dump the signals.
    >
    > vcd file dump.vcd
    > vcd add /top/* /*I assume this means dump all signals */
    >
    > I can see real signals in the wlf format of Modelsim but not in the VCD format
    > in which am trying to dump the signals.
    >
    > Thanks and Regards,
    > Sajan.
     
    Ajeetha Kumari, Sep 23, 2003
    #5
  6. Sajan

    Sajan Guest

    Hi
    Thanks for the effort.
    I am modeling a Digital to analog converter in VHDL and the output of
    the module is expected to be a real signal which is a sinewave.
    I want to see the sinewave in the waveform. Somehow modelsim wave
    window does not show a smooth transition from one signal level to the
    other. So I want to dump it in VCD and then open it using other
    waveform viewer like signal-scan.
    Well thats the basic idea.
    Cheers,
    Sajan.

    (Ajeetha Kumari) wrote in message news:<>...
    > Sajan,
    > You seem to be correct, some how the "vcd add" misses out real
    > signals in VHDL. Initially I tried a Verilog example, that worked fine
    > with vcd add command. Looks like only the VHDL part of it has some
    > issue.
    >
    > Sorry, couldn't be of much help, perhaps contact Modelsim support? Why
    > do you prefer VCD against WLF?
    >
    > > vcd add /top/* /*I assume this means dump all signals */
    > >

    >
    > This adds all signals in top instance, use with -r if you want the
    > whole hierarchy (I guess you know that already).
    >
    > Ajeetha
    > http://www.noveldv.com
    >
    > (Sajan) wrote in message news:<>...
    > > Hi
    > > I am using VHDL.
    > > I use the following commands in the modelsim commandline
    > > interface to dump the signals.
    > >
    > > vcd file dump.vcd
    > > vcd add /top/* /*I assume this means dump all signals */
    > >
    > > I can see real signals in the wlf format of Modelsim but not in the VCD format
    > > in which am trying to dump the signals.
    > >
    > > Thanks and Regards,
    > > Sajan.
     
    Sajan, Sep 23, 2003
    #6
  7. Sajan

    Alan Fitch Guest

    "Sajan" <> wrote in message
    news:...
    > Hi
    > Thanks for the effort.
    > I am modeling a Digital to analog converter in VHDL and the output

    of
    > the module is expected to be a real signal which is a sinewave.
    > I want to see the sinewave in the waveform. Somehow modelsim wave
    > window does not show a smooth transition from one signal level to

    the
    > other.


    Have you tried selecting "analog interpolated" in Modelsim?

    regards

    Alan

    --
    Alan Fitch
    Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
    Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
    1AW, UK
    Tel: +44 (0)1425 471223 mail:

    Fax: +44 (0)1425 471573 Web:
    http://www.doulos.com

    The contents of this message may contain personal views which are not
    the
    views of Doulos Ltd., unless specifically stated.
     
    Alan Fitch, Sep 23, 2003
    #7
  8. Sajan

    Sajan Guest

    Thanks , I didnt know about that option.
    Am able to get what I need using interpolated option.

    Regards,
    Sajan.

    "Alan Fitch" <> wrote in message news:<bkpot6$ih7$1$>...
    > "Sajan" <> wrote in message
    > news:...
    > > Hi
    > > Thanks for the effort.
    > > I am modeling a Digital to analog converter in VHDL and the output

    > of
    > > the module is expected to be a real signal which is a sinewave.
    > > I want to see the sinewave in the waveform. Somehow modelsim wave
    > > window does not show a smooth transition from one signal level to

    > the
    > > other.

    >
    > Have you tried selecting "analog interpolated" in Modelsim?
    >
    > regards
    >
    > Alan
    >
    > --
    > Alan Fitch
    > Consultant
    >
    > DOULOS - Developing Design Know-how
    > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
    > Services
    >
    > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
    > 1AW, UK
    > Tel: +44 (0)1425 471223 mail:
    >
    > Fax: +44 (0)1425 471573 Web:
    > http://www.doulos.com
    >
    > The contents of this message may contain personal views which are not
    > the
    > views of Doulos Ltd., unless specifically stated.
     
    Sajan, Sep 24, 2003
    #8
  9. Sajan

    vlsi.engg27

    Joined:
    Jul 20, 2007
    Messages:
    1
    help needed

    hi ajeetha

    read abt u lot on the net

    i hpe u can solve my problem related to assertions(sva)

    is there any way where i can dump all my signals.and then write assertions say (ex for simple arbiter) and then check for assertion pass/fail..currently am using synopsys vcs simulator.if u have ans to my question plz can u mail me in detail to

    thanks
     
    vlsi.engg27, Jul 21, 2007
    #9
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