Dumping real signals in VCD

[Sajan]

Hi
I am dumping signals which are declared as integer and real.
But i cant find these signals in the dump file.
Can anyone tell me why this happens and how to over this.
Regards,
Sajan.

 

[Sajan]

Well i forgot to mention that I am using Modelsim to do this.

 

[Ajeetha Kumari]

Sajan,
Not sure if you are talking about VHDL or Verilog, either way
Modelsim can
probe real signals/variables in its waveform. When you say "VCD" how
do you create your VCD? That may be where the problem is, can you show
us how you dump VCD?

Ajeetha
http://www.noveldv.com

 

[Sajan]

Hi
I am using VHDL.
I use the following commands in the modelsim commandline
interface to dump the signals.

vcd file dump.vcd
vcd add /top/* /*I assume this means dump all signals */

I can see real signals in the wlf format of Modelsim but not in the VCD format
in which am trying to dump the signals.

Thanks and Regards,
Sajan.

 

[Ajeetha Kumari]

Sajan,
You seem to be correct, some how the "vcd add" misses out real
signals in VHDL. Initially I tried a Verilog example, that worked fine
with vcd add command. Looks like only the VHDL part of it has some
issue.

Sorry, couldn't be of much help, perhaps contact Modelsim support? Why
do you prefer VCD against WLF?

vcd add /top/* /*I assume this means dump all signals */

This adds all signals in top instance, use with -r if you want the
whole hierarchy (I guess you know that already).

Ajeetha
http://www.noveldv.com

 

[Sajan]

Hi
Thanks for the effort.
I am modeling a Digital to analog converter in VHDL and the output of
the module is expected to be a real signal which is a sinewave.
I want to see the sinewave in the waveform. Somehow modelsim wave
window does not show a smooth transition from one signal level to the
other. So I want to dump it in VCD and then open it using other
waveform viewer like signal-scan.
Well thats the basic idea.
Cheers,
Sajan.

 

[Alan Fitch]

Hi
Thanks for the effort.
I am modeling a Digital to analog converter in VHDL and the output of
the module is expected to be a real signal which is a sinewave.
I want to see the sinewave in the waveform. Somehow modelsim wave
window does not show a smooth transition from one signal level to the
other.

Have you tried selecting "analog interpolated" in Modelsim?

regards

Alan

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[Sajan]

Thanks , I didnt know about that option.
Am able to get what I need using interpolated option.

Regards,
Sajan.

 

[vlsi.engg27]

help needed

hi ajeetha

read abt u lot on the net

i hpe u can solve my problem related to assertions(sva)

is there any way where i can dump all my signals.and then write assertions say (ex for simple arbiter) and then check for assertion pass/fail..currently am using synopsys vcs simulator.if u have ans to my question plz can u mail me in detail to (e-mail address removed)

thanks