Error in FIFO Simulation ISE Xilinx

Discussion in 'VHDL' started by nfirtaps, Aug 31, 2006.

  1. nfirtaps

    nfirtaps Guest

    Hello, I am simulating a FIFO in ISE generated by CORGEN. The design
    synthesizes and no errors or warnings indicate I have done anything
    wrong. I am doing this simulation for a Spartan3E which is indicated
    in my design summary. However, when I try to simulate I get the
    following error:

    ** Failure:FAILURE: Use of behavioral models for Virtex-4 and Virtex-5
    built-in FIFO configurations is currently not supported. Please use the
    structural simulation model. You can enable this from CORE Generator by
    selecting Project -> Project Options -> Generation tab -> Structural
    Simulation. See the FIFO Generator User Guide for more information.
    User(VHDL) Code Called Simulation Stop

    I am not targeting a Virtex part anywhere so I have no idea why this
    error would occur?

    Is there any advice out there for what I (or most likely as usual ISE)
    is doing wrong?

    Thanks
    nfirtaps, Aug 31, 2006
    #1
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  2. nfirtaps wrote:
    > Hello, I am simulating a FIFO in ISE generated by CORGEN.
    > I am not targeting a Virtex part anywhere so I have no idea why this
    > error would occur?


    Coregen is a Xilinx thing, not a VHDL thing.

    > Is there any advice out there for what I (or most likely as usual ISE)
    > is doing wrong?


    The VHDL solution would be to
    infer a dpram from a code template
    and write code describing head (read only)
    and tail (write only) address counters.

    -- Mike Treseler
    Mike Treseler, Aug 31, 2006
    #2
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