FIR Coefficients

Discussion in 'VHDL' started by RealInfo, Feb 2, 2009.

  1. RealInfo

    RealInfo Guest

    Hi all

    The coefficients used in FIRs , what representation they are in ?
    REAL, SIGNED , POSITIVE etc ?

    I ask this because I wonder if I can design a FIR without RTL description of
    the mulitpliers
    just the " D_out_n * Coef_n " form and rely on the synthesiser that it will
    "understand" my meaning and generate the right netlist for the multipliers.
    for this to happen I have to define the coef's in the proper representation
    ..

    Thanks in advance

    EC
     
    RealInfo, Feb 2, 2009
    #1
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  2. RealInfo

    Guest

    On Feb 2, 9:30 am, "RealInfo" <> wrote:
    > Hi all
    >
    > The coefficients used in FIRs , what representation they are in ?
    > REAL, SIGNED , POSITIVE etc ?
    >
    > I ask this because I wonder if I can design a FIR without RTL description of
    > the mulitpliers
    > just the  " D_out_n * Coef_n " form and rely on the synthesiser that it will
    > "understand" my meaning and generate the right netlist for the multipliers.
    > for this to happen I have to define the coef's in the proper representation
    > .
    >
    > Thanks in advance
    >
    > EC


    Usually, coefficients will be a mixture of positive and negative, so
    POSITIVE won't work. Most FPGA implementations of FIR filters express
    the whole filter as being scaled by a power of two, meaning that you
    multiply your (real) impulse response by 2^N and then right-shift your
    output by N bits (effectively dividing by 2^N) to renormalize it.
    After multiplying by 2^N you round to integer values, giving an
    approximation to the original filter with some rounding error due to
    this quantization. I'd suggest also taking a read through the much-
    cited presentation

    http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

    You can get the synthesizer to do a lot of the work by using the right
    types, as you're hoping, but to get decent performance you'll still
    have to think about the pipelining and cycle-by-cycle dataflow.

    - Kenn
     
    , Feb 2, 2009
    #2
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  3. RealInfo

    RealInfo Guest

    Many thanks
    EC


    <> ???
    ??????:...
    On Feb 2, 9:30 am, "RealInfo" <> wrote:
    > Hi all
    >
    > The coefficients used in FIRs , what representation they are in ?
    > REAL, SIGNED , POSITIVE etc ?
    >
    > I ask this because I wonder if I can design a FIR without RTL description
    > of
    > the mulitpliers
    > just the " D_out_n * Coef_n " form and rely on the synthesiser that it
    > will
    > "understand" my meaning and generate the right netlist for the
    > multipliers.
    > for this to happen I have to define the coef's in the proper
    > representation
    > .
    >
    > Thanks in advance
    >
    > EC


    Usually, coefficients will be a mixture of positive and negative, so
    POSITIVE won't work. Most FPGA implementations of FIR filters express
    the whole filter as being scaled by a power of two, meaning that you
    multiply your (real) impulse response by 2^N and then right-shift your
    output by N bits (effectively dividing by 2^N) to renormalize it.
    After multiplying by 2^N you round to integer values, giving an
    approximation to the original filter with some rounding error due to
    this quantization. I'd suggest also taking a read through the much-
    cited presentation

    http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

    You can get the synthesizer to do a lot of the work by using the right
    types, as you're hoping, but to get decent performance you'll still
    have to think about the pipelining and cycle-by-cycle dataflow.

    - Kenn
     
    RealInfo, Feb 2, 2009
    #3
    1. Advertising

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