fixed point in VHDL

Discussion in 'VHDL' started by sanborne, Dec 4, 2008.

  1. sanborne

    sanborne Guest

    I am a relatively new user of VHDL, but I have never before needed to
    use fixed point data for VHDL that can be synthesized. What are the
    best options in this regard? What are peoples experiences?

    I did a google search, and there are a lot of different alternatives,
    but I am not sure if there is a standard. And I am not sure which of
    the options can be synthesized. The package that looks most promising
    can be found at:

    http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/fixed_pkg_c.vhdl

    Are there any issues with this package?

    Thanks for any pointers or suggestions.

    SY
    sanborne, Dec 4, 2008
    #1
    1. Advertising

  2. sanborne

    Tricky Guest

    sanborne wrote:

    > I am a relatively new user of VHDL, but I have never before needed to
    > use fixed point data for VHDL that can be synthesized. What are the
    > best options in this regard? What are peoples experiences?
    >
    > I did a google search, and there are a lot of different alternatives,
    > but I am not sure if there is a standard. And I am not sure which of
    > the options can be synthesized. The package that looks most promising
    > can be found at:
    >
    > http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/fixed_pkg_c.vhdl
    >
    > Are there any issues with this package?
    >
    > Thanks for any pointers or suggestions.
    >
    > SY


    There are libraries available to held people out with fixed point, but
    these are not universally supported and Afaik, not yet standardised
    (though I think they will be in upcoming VHDL revsions). But
    standardisation doesnt neccasrily mean it will be supported.

    The best thing to remember about fixed point is that it is no
    different to normal signed/unsigned arithmatic. The same adders/
    multipliers get used for both. The trick come in working out where the
    separation lies. All fixed point is is the "normal" value of the
    binary representation divided by 2^n. Each bit to the right of the
    point is 2^(-n)

    Lets take a quick unsigned example, using 6 bits (4 bits magnitude, 2
    bits fraction):

    4.25 + 7.75 = 12.00

    In binary, these are represented as
    0100.01 + 0111.11 = 1100.00

    Taken another way, this is:

    (17+ 31 = 48)/4. The /4 is an implied divide by 4 and not actually
    done.

    Multiplication is again identical to "normal" arithmatic. Its all
    about where you actually take the result:

    lets take the same values, 4.25 * 7.75

    using the binary, we get 0100.01 * 0111.11 . we just forget the . and
    do normal binary multiplication. The same rule applies - a 6 bit
    number * 6 bit number gives a 12 bit result. But because we have a
    point, its now a 4.2 number x a 4.2 number, which gives a 8.4 result

    So normal binary addition:

    0 1 1 1 1 1 0 0 0 0 2^4 x 7.75
    + 0 1 1 1 1 1 2^0 x 7.75
    ---------------------------------
    1 0 0 0 0 0 1 1 1 1 32.9375 (527 / 2^4)

    This is 2^5 + 2^(-1) + 2^(-2) + 2^(-3) + 2^(-4)

    All of this applies equally to signed arithmatic. It is all no
    different to standard arithmatic. but remember 2s compliment is now
    invert all the bits and add 2^(-n) instead of 1, but again its not
    different.

    Clever tricks can also be done.

    Take this example, using only a 4 bit miltipliers to get a 4 bit
    (rounded) result. We will assume the 2nd input is always < 1

    15 * 0.9375 = 14.0625

    1111.0000 * 00001111

    We can ignore the top 4 bits of 0.9375, because we know, as it is
    always <1. We also ignore the bottom 4 bits of 15, because we will
    assume it never has any fractional components.

    so we can use the hardware multipler with these 2 inputs:

    1111 * 1111

    But we know that the left one is 4.0 number, and the right is a 0.4
    number. this means that our 8 bit output is a 4.4 number.

    1 1 1 1
    1 1 1 1
    1 1 1 1
    + 1 1 1 1
    ----------------------------
    1 1 1 0 . 0 0 0 1 = 14.0625

    If you were tied to a 4bit output, you would need to round the values.
    So you would then + 0.5:

    1 1 1 0 . 0 0 0 1
    +0 0 0 0 . 1 0 0 0
    ---------------------------
    1 1 1 0 . 1 0 0 1 = 14.5625

    And then chop the last 4 bits off, to get 1110 (14) to get your result.
    Tricky, Dec 4, 2008
    #2
    1. Advertising

  3. sanborne

    Tricky Guest

    On 4 Dec, 17:41, Jim Lewis <> wrote:
    > All,
    > Please note that David's links are the correct links to use:
    >    http://www.vhdl.org/fphdl/vhdl.html
    >
    > If you use the old vhdl-200x-ft links to the old files, an error
    > handler will now tell you were to go :) to find the new files
    >
    > Cheers,
    > Jim
    >
    >
    >
    > > sanborne wrote:
    > >> I am a relatively new user of VHDL, but I have never before needed to
    > >> use fixed point data for VHDL that can be synthesized. What are the
    > >> best options in this regard? What are peoples experiences?

    >
    > >> I did a google search, and there are a lot of different alternatives,
    > >> but I am not sure if there is a standard. And I am not sure which of
    > >> the options can be synthesized. The package that looks most promising
    > >> can be found at:

    >
    > >>http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/fixed_pkg_c.vhdl

    >
    > >> Are there any issues with this package?

    >
    > >> Thanks for any pointers or suggestions.

    >
    > > You will want to use the packages which have been modified for your
    > > tool.  You will find a list here:
    > >http://www.vhdl.org/fphdl/vhdl.html

    >
    > > The packages work in "most" tools.   Xilinx ISE 10 does not work,
    > > however I have been promised that it will work in Verion 11 (which I
    > > found out today will be licensed under FlexLM!).  I use Synplicity to
    > > synthesize to Xilinx parts anyway.

    >
    > > I use these packages in my ASIC and FPGA designs.  They work well for
    > > me.  However, I'm the guy that wrote them.

    >
    > --
    > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    > Jim Lewis    SynthWorks VHDL Training    http://www.synthworks.com
    >
    > A bird in the hand may be worth two in the bush,
    > but it sure makes it hard to type.


    Sorry for being a bit negative before.

    Just downloaded and had a play. I dont think Ill be going back :)
    Tricky, Dec 4, 2008
    #3
  4. sanborne

    vipinlal

    Joined:
    Feb 25, 2010
    Messages:
    38
    Read tutoRial seRies on fixed point vhdl package heRe..
    vhdlguru.blogspot.com/2010/03/fixed-point-operations-in-vhdl-tutorial.html
    vipinlal, Mar 29, 2010
    #4
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Viswan
    Replies:
    9
    Views:
    12,023
    Ray Andraka
    Feb 11, 2004
  2. H aka N
    Replies:
    15
    Views:
    15,607
    Ben Jones
    Mar 2, 2006
  3. Motaz Saad
    Replies:
    7
    Views:
    6,456
  4. Replies:
    4
    Views:
    1,270
    Default User
    Feb 22, 2006
  5. Saraswati lakki
    Replies:
    0
    Views:
    1,284
    Saraswati lakki
    Jan 6, 2012
Loading...

Share This Page