Flex model concept?

[MM]

I am trying to understand the VHDL structure behind one of the Synopsys flex
models:
(http://www.synopsys.com/products/designware/docs/ds/s/ieee1394a_fx.pdf).
I don't have access to the model itself, only to this datasheet... There is
a VHDL testbench example in this datasheet that shows how the model is
instantiated. Can someone please explain how they did the command interface?
Are these commands (shown in red in the testbench example) VHDL procedures?
If they are how do they communicate to the model? I guess it happens somehow
through a handle, but how do you do it in VHDL? I am intrigued by this
concept...

Thanks,
/Mikhail

 

[Mike Treseler]

Are these commands (shown in red in the testbench example) VHDL procedures?

pg 50
http://www.synopsys.com/products/designware/docs/doc/smartmodel/manuals/flexum.pdf

-- Mike Treseler

 

[MM]

procedures?

pg 50
http://www.synopsys.com/products/designware/docs/doc/smartmodel/manuals/flexum.pdf

OK, I see. It seems that the thing is pretty complicated and involves much
more than just VHDL language, requires a simulator with SWIFT interface,
etc. Is the whole point of this to hide the model implementation in a binary
or are there other reasons? Assuming I wanted to do a functionally similar
thing, I guess I could simply add a command control port to the model entity
and have it controlled by external procedures the way I wanted. Is there a
downside to this approach compared to what Synopsys offers (besides hiding
the implementation)?

/Mikhail

 

[Mike Treseler]

etc. Is the whole point of this to hide the model implementation in a binary
or are there other reasons?

That would be my guess.

Assuming I wanted to do a functionally similar
thing, I guess I could simply add a command control port to the model entity
and have it controlled by external procedures the way I wanted.

Yes, keep it simple; have it your way.

Is there a
downside to this approach compared to what Synopsys offers (besides hiding
the implementation)?

Unless you already own and must use this model,
there is no reason to study this odd interface.

-- Mike Treseler

 

[MM]

Thanks, Mike. I feel more confident now...

/Mikhail