FPGA interface design to access the BRAM

Discussion in 'VHDL' started by pingluns@gmail.com, Jan 10, 2006.

  1. Guest

    Hi guys:

    Currently I am try to design a interface between PPC, FPGA and BRAM.
    Because it is my first time working on the FPGA design, can anyone give
    me some idea about how to design the interface between BRAM and FPGA?
    In my the design, FPGA needs to access the shared BRAM (share with PPC)
    and read the data from a memory address and write the data back to the
    BRAM once it finishes.






    WilliamS
     
    , Jan 10, 2006
    #1
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