Free Verilog Simulator

[ngsayjoe]

Hi All Verilogers,


I recently developed a new Verilog Simulator and it's free for the time

being. I'd like to get some users to use it and hope for some valuable
feedbacks. The current release (v1.4) is still not very stable yet,
however it can support most of the basic Verilog constucts. But some
advanced features such as "generate" is yet to be supported. It's
available for download at http://www.logicsim.com and it's currently
named LogicSim.


The current release is only available on WindowsXP platform, however I
plan to port it to Linux once the release is stable. Besides, I'm
working on some basic SystemVerilog support, since it's the superset of

SystemVerilog, hence a full support wouldn't be that difficult. Of
course that is the long term goal as, the SystemVerilog standard
1800-2005 is a huge standard, it will take some time to reach there.
Thanks.


Thanks,
Joe

 

[kameshwar_kaushik]

LogicSim

Hey man,
i usually use ModelSim. But i've give ur software a try. Congrats on ur software man. I hope, i'd get a free version of yer software since i m a beta-tester of yer software

 

[ngsayjoe]

Sure, as long as you report quality bugs, you'll be entitled for a free version once we release LogicSim 2.0. The current schedule for v2.0 is March 2007, we promise it's going to be the best, cheapest and most user-friendly Verilog Simulator on the market.