generate testbench for array signals

[Simone Winkler]

Hey there,

i tried to generate a testbench waveform with Xilinx ISE Software - but it
seems that it doesnt support array types.... (it wants me to use either bit,
bit_vector or integer).
i'm using ISE 4.2 - does somebody know if this is better in version 5.2?

Thanx,
Simone

 

[Pedro Claro]

Hey there,

i tried to generate a testbench waveform with Xilinx ISE Software - but it
seems that it doesnt support array types.... (it wants me to use either bit,
bit_vector or integer).
i'm using ISE 4.2 - does somebody know if this is better in version 5.2?

Thanx,
Simone

Hi,

What do you mean with array type in signals? Like std_logic_vector[X
downto 0] ?
If you mean giving values to signals in an automatic way try putting
commas, like: (example of a 16 bit signal ) FF,01,A1,B1, etc.


I upgraded from Xilinx ISE 4.2 to 5.1. I sticked with 5.1 because when
installing 5.2 I had troubles with licenses. I believe that 5.1 is
better than 4.2. But that's only my opinion.


Pedro Claro