Generic Component Instantiation

Discussion in 'VHDL' started by minhajhassan, Sep 26, 2008.

  1. minhajhassan

    minhajhassan

    Joined:
    Sep 26, 2008
    Messages:
    1
    I am instantiating a module N number of times, each time with different parameters as shown

    Gen_LUTs: for i in 0 to N-1 generate
    LUTs: LUT_generic generic map (LUT_Size(i),Log_Size(i),LUT_Width(i))
    port map(....
    Where LUT_Size, Log_Size, LUT_Width are arrays of integers.
    The port sizes of IN/Outs depends upon the generics

    How should the component be instantiated in the declarative part. Without i.
    If not possible is there any better way to do this?
     
    minhajhassan, Sep 26, 2008
    #1
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