how to convert real type to std_logic_vector ?

Discussion in 'VHDL' started by jing, May 17, 2006.

  1. jing

    jing Guest

    i'm a beginner in vhdl. please tell me how to convert real type to
    std_logic_vector ?
    i wrote as:

    process
    variable input_line : line;
    variable input_data : real;
    begin
    i <= 0;
    xn_re <= "0000000000000000";

    while not endfile(DATA_FILE) loop
    readline(DATA_FILE, input_line);
    read(input_line, input_data);

    xn_re <= std_logic_vector(to_signed(integer(input_data),
    16));-----here is the problem,but if i use xn_re <=
    conv_std_logic_vector(input_data, 16); the input_data should not be a
    real type....., then i don't know how to solve it.....

    thank you in advace!
    jing, May 17, 2006
    #1
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  2. Mike Treseler, May 17, 2006
    #2
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