# How to generate a signal that will remain high for 687500 clock cycles ?

Discussion in 'VHDL' started by tarek, Mar 29, 2009.

1. ### tarek

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Mar 21, 2009
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Hi everyone,

I am required to generate a signal that will remain high for 687500 clock cycles and then goes low for 16 clock cycles and the sequence is repeated.

Can anyone help

Thank you,
Tarek

tarek, Mar 29, 2009

2. ### JohnDuq

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Dec 9, 2008
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That looks like a simple case in a process

if (X < 687500) out = 1 else out = 0

If x > 687516 then x = 0
X <= X + 1;

that isn't VHDL coding but it conveys the idea.

John

JohnDuq, Mar 30, 2009

3. ### JohnDuq

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Dec 9, 2008
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Or if your clock is fixed you can use a technique like this:

CLK <= '0';
wait for (PERIOD - (PERIOD * DUTY_CYCLE));
CLK <= '1';
wait for (PERIOD * DUTY_CYCLE);

This is straight out of the VHDL simulation templates in Xilinx ISE. You never stated whether you were trying to simulate or synthesize this function.

John

JohnDuq, Mar 30, 2009
4. ### tarek

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Mar 21, 2009
Messages:
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Thanks a lot John,

I actually required it for synthesis... Anyway here is the code i wrote for counting till 100 and it is working perfectly.

Thank you again for your help
----------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity Counter is
Port ( CLK : in STD_LOGIC;
Output : out STD_LOGIC);
end Counter;

architecture Behavioral of Counter is

signal count: std_logic_vector(7 downto 0):= (others => '0');

begin

process (CLK)
begin

if rising_edge(CLK) then
if count < "01100100" then --100
Output<= '1';
else
Output <= '0';
end if;

if count >"01110100" then -- 116
count <= (others =>'0');
else
count <= count + '1';
end if;
end if;
end process;
----------------------------------------------

tarek, Mar 31, 2009

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