I2C master connected and tested with LEON Processor

Discussion in 'VHDL' started by Pinhas, Aug 10, 2007.

  1. Pinhas

    Pinhas Guest

    This design uses the open core's I2C master. The core's CPU interface
    is

    modified from WISHBONE to AMBA/APB. The latter is done in order to
    test the

    core and its new APB interface with LEON processor. LEON is written in
    VHDL

    therefor the core's VHDL RTL design is tested.

    The core also contains a test bench and simulation model for slave,
    written in

    VERILOG. From the VERILOG test bench only the initialization procedure
    is taken and the I2C slave model is translated to VHDL.

    http://bknpk.no-ip.biz/I2C/leon_2.html
    http://bknpk.no-ip.bi
     
    Pinhas, Aug 10, 2007
    #1
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