Interactive Active HDL testbench creator

Discussion in 'VHDL' started by luca_grossi@hotmail.com, Oct 30, 2006.

  1. Guest

    Hi All,
    I was wondering is it possible to create a VHDL testbench interactively
    using Active HDL? Similar to what is available with Xilinx ISE. If not
    , are their any other methods of achieving something similar via other
    means ?

    Cheers Luca
     
    , Oct 30, 2006
    #1
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