Is this an LRM thing, or Modelsim Bug?

[Tricky]

Ive got this code:

library ieee;
use ieee.std_logic_1164.all;

entity play_TB is
generic (
DEBUG : boolean := true
);


end entity;

architecture rtl of play_TB is
signal test : std_logic;
begin


process
begin
if DEBUG then
test <= '0';
end if;

wait;
end process;

test <= '1';

end rtl;

This quite correctly has test set to 'X' when the simulation runs.

But if DEBUG is false, test remains at 'U'.

So is this an LRM thing, or is it a modelsim bug?

 

[Jonathan Bromley]

Ive got this code:

library ieee;
use ieee.std_logic_1164.all;

entity play_TB is
generic (
DEBUG : boolean := true
);


end entity;

architecture rtl of play_TB is
signal test : std_logic;
begin


process
begin
if DEBUG then
test <= '0';
end if;

wait;
end process;

test <= '1';

end rtl;

This quite correctly has test set to 'X' when the simulation runs.

But if DEBUG is false, test remains at 'U'.

So is this an LRM thing, or is it a modelsim bug?

I'm sure that's correct per LRM. Your process represents a
driver on 'test'. If you choose, at runtime, not to write
to 'test' then the driver will stay at its default value
of 'U'.

If you use generic DEBUG to if-generate the process, then
of course the driver will disappear completely if DEBUG
is false.

You could also consider initializing 'test' to 'Z' somewhere;
perhaps in its declaration (so *all* drivers start at 'Z')
or at the start of the process, independent of the value
of DEBUG (in which case the driver will be 'U' for the first
delta cycle).

 

[Martin Thompson]

Ive got this code:

process
begin
if DEBUG then
test <= '0';
end if;

wait;
end process;

This process has a driver in it. When DEBUG is false, that driver
doesn't get any assignments to change it from its default state of 'U'.

You could either initialise the signal, or provide a default driver (maybe
to 'Z') in the process, or if..generate the whole process (which removes
the driver as well)

Cheers,
Martin