Is transaction-based debugging useful ?

Discussion in 'VHDL' started by ben cohen, Aug 20, 2003.

  1. ben cohen

    ben cohen Guest

    (VhdlCohen) wrote in message news:<>...
    > >Cadence has pushed the transaction-based debugging concept for
    > >many years, but it looks like many designers do not accept this
    > >methodology, could some people out there explain the reasons ?
    > >
    > >

    > I like transaction-based modeling for TB because the model distinguishes btween
    > JOBs or transactions, and low-level interface signals. I used
    > trasnsaction-based modeling with Verilog and VHDL, but not with Testbuilder.
    > You can read a white paper at my site, under models and papers.
    >
    > veriflang.pdf Document: Transaction-Based Verification in HDL
    > Ben Cohen

    --
    >In actual scenario, in some cases, there could be lot of transactions
    >not exactly initiated by testbench. There could be protocol

    violations
    >during this time when the testbench is transaction based. I suggest
    >protocol checker followed by a transaction based testbench.
    >

    The TB reacts to the environment. Thus, if the Device Under Test
    (DUT)
    has a protocol violation casues by correct design (e.g., a mode), then
    the TB
    should react accordingly. Transaction-based means the following to
    me.
    1. TB_Client issues a transaction (a task) to a server.
    2. Server interprets the task (e.g., READ), and issues the low-level
    protocol for the READ.
    3. DUT replies using low level protocol.
    4. Server collects the received data, using the low-level protocol,
    and creates a REPLY transaction to TB_Client.
    5. TB_CLient may react to the REPLY transaction according to
    requirements.

    Now for the checkers: If you use an HDL checker, the checkers reads
    the TB_Client and REPLY transactions and dtermines accuracy of
    results. A scoreboard may be used by teh checker.

    If you use ABV with PSL, you write assertions in your RTL code that
    performs during simulation white-box verification. ABV with PSL can
    also be used for formal verification without simulation.

    How many client/servers do you need, That depends upon the DUT.
    In my book "Component Design by Example", I used 2, one set for each
    interface of the UART (XMT and RCV).

    MY latest book on PSL demosntrates applications of PSL for simulation.
    However, the same code with additional verification directives can be
    used for fomal verification.
    ABV is the new paradigm shift for verification, just like computer
    synthesis from RTL was a shift from manual synthesis with schematics.

    ----------------------------------------------------------------------------
    Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
    http://www.vhdlcohen.com/
    Author of following textbooks:
    * Using PSL/SUGAR with Verilog and VHDL
    Guide to Property Specification Language for ABV, 2003 isbn
    0-9705394-4-4
    * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
    0-9705394-2-8
    * Component Design by Example ", 2001 isbn 0-9705394-0-1
    * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
    0-7923-8474-1
    * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
    0-7923-8115
    ------------------------------------------------------------------------------
    ben cohen, Aug 20, 2003
    #1
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