ISE problem - multiplier inputs on schematic are not assigned correctly.

[AndyAtHome]

Hi,

I'm using Xilinx ISE 6.2.02 Base-X.

If I synthesize example 1, and view the schematic, the inputs to the
multiplier are not assigned by name to the input signals, it just
shows A<L:R> and B<L:R>.

However Modelsim says the circuit works, so hey I'm guessing the
inputs to the multiplier are actually assigned (to J and ROWLEN
signals)

However if I add an addition operator (as in example 2), and view the
schematic, the multiplier inputs are now shown assigned correctly.

Is this a bug? Wisdom and advice appreciated...

Andy.



EXAMPLE 1
---------

entity PIPE_ACU is
port(
CLK : in STD_LOGIC;
CE: in STD_LOGIC;
ROWLEN: in STD_LOGIC_VECTOR(7 downto 0);
--I: in STD_LOGIC_VECTOR(7 downto 0);
J: in STD_LOGIC_VECTOR(7 downto 0);
ADDR: out STD_LOGIC_VECTOR(15 downto 0)
);
end PIPE_ACU;

architecture Behavioral of PIPE_ACU is

begin

C1: process (CLK) is
begin
if CLK'event and CLK = '1' then
if CE = '1' then

--ADDR <= (J * ROWLEN) + I;
ADDR <= J * ROWLEN;

end if;
end if;

end process;


end Behavioral;

EXAMPLE 2
---------

entity PIPE_ACU is
port(
CLK : in STD_LOGIC;
CE: in STD_LOGIC;
ROWLEN: in STD_LOGIC_VECTOR(7 downto 0);
I: in STD_LOGIC_VECTOR(7 downto 0);
J: in STD_LOGIC_VECTOR(7 downto 0);
ADDR: out STD_LOGIC_VECTOR(15 downto 0)
);
end PIPE_ACU;

architecture Behavioral of PIPE_ACU is

begin

C1: process (CLK) is
begin
if CLK'event and CLK = '1' then
if CE = '1' then

ADDR <= (J * ROWLEN) + I;
--ADDR <= J * ROWLEN;

end if;
end if;

end process;


end Behavioral;

 

[AndyAtHome]

I opened a case with Xilinx... it's a bug in ECS in ISE 6.2.

Andy.