Hi,
I am using Xilinx AccelDSP to convert my matlab code to VHDL and Synthesize, etc. Now I have a critical path which didn't meet the timing constraint. I know that insert pipestage can be used to speedup the working frequency, however, I am confused about if loop or operation unroll can also be used to breakdown the critical path and speedup the frequency?
anybody could give me a hand? thanks in advance.
I am using Xilinx AccelDSP to convert my matlab code to VHDL and Synthesize, etc. Now I have a critical path which didn't meet the timing constraint. I know that insert pipestage can be used to speedup the working frequency, however, I am confused about if loop or operation unroll can also be used to breakdown the critical path and speedup the frequency?
anybody could give me a hand? thanks in advance.