maximum clock speed so that a design can safely operate

Discussion in 'VHDL' started by benn, Mar 12, 2005.

  1. benn

    benn Guest

    Hi guys, im pretty new to quartus and i was just wondering how t
    calculate the maximum clock speed so that a design can safely operate
    Any help would be greatly appreciated.

    Thank you in advanc

    --
    bennwww.totallychips.com - VHDL, Verilog & General Hardware Design discussion Foru
    benn, Mar 12, 2005
    #1
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  2. benn wrote:
    > Hi guys, im pretty new to quartus and i was just wondering how to
    > calculate the maximum clock speed so that a design can safely operate.
    > Any help would be greatly appreciated.


    In the default flow, quartus runs a
    static timing analysis which gives
    you this information.

    -- Mike Treseler
    Mike Treseler, Mar 12, 2005
    #2
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  3. benn

    Neo Guest

    Or you just punch in an arbitrary clock frequency(say 10 Mhz) and run
    the tool. the results will give you the actual possible clock freq for
    your design.
    Neo, Mar 14, 2005
    #3
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