Mixed VHDL/Verilog + defparam

Discussion in 'VHDL' started by Hans, Jul 27, 2004.

  1. Hans

    Hans Guest

    Hi,

    Can anybody tell me how to instantiate a verilog netlist + annotate module
    (defparam) in a VHDL testbench?

    I have created a simple testcase:

    -- VHDL TestBench instantiating Verilog Module
    use ieee.std_logic_1164.all;
    entity tb is
    end tb;
    architecture arch of tb is
    component test
    end component;
    begin
    uut: test;
    end arch;

    -- Verilog Module and Annotate Module
    module test;
    wire w;
    block b1 ();
    endmodule

    module block;
    parameter p=1;
    endmodule

    module annotate;
    defparam test.b1.p=2; // works for Verilog only
    //defparam tb.uut.test.b1.p=2; //fails
    //defparam /tb/uut.test.b1.p=2; //fails
    //defparam /tb/uut/test.b1.p=2; //fails
    endmodule


    If I just load the verilog module it works fine (using Modelsim):

    vlog test.v
    vsim -c test annotate
    examine sim:/test/b1/p -> p=2!

    Instantiating the Verilog test module in a VHDL testbench is no problem,
    however, how to update the parameter 'p'?

    If I use:

    vlog test.v
    vcom tb.vhd
    vsim -c tb annotate

    I get: * Error: (vsim-3043) test.v(12): Unresolved reference to 'test' in
    test.b1.p.


    I then tried several defparam permutations all without any luck. If you take
    out the annotate module the simulation runs fine but with p=1.

    I suspect that you can not reference a parameter through a VHDL entity but I
    just want to make sure that is the case,

    Thanks,
    Hans.
     
    Hans, Jul 27, 2004
    #1
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  2. Hans

    Hans Guest

    The solution is simple, just call the annotate from the test module as in:

    module test;
    wire w;
    block b1 ();
    annotate annotate();
    endmodule


    No were is that beginners guide to verilog..... :)

    Hans.


    "Hans" <> wrote in message
    news:ezpNc.186$...
    > Hi,
    >
    > Can anybody tell me how to instantiate a verilog netlist + annotate module
    > (defparam) in a VHDL testbench?
    >
    > I have created a simple testcase:
    >
    > -- VHDL TestBench instantiating Verilog Module
    > use ieee.std_logic_1164.all;
    > entity tb is
    > end tb;
    > architecture arch of tb is
    > component test
    > end component;
    > begin
    > uut: test;
    > end arch;
    >
    > -- Verilog Module and Annotate Module
    > module test;
    > wire w;
    > block b1 ();
    > endmodule
    >
    > module block;
    > parameter p=1;
    > endmodule
    >
    > module annotate;
    > defparam test.b1.p=2; // works for Verilog only
    > //defparam tb.uut.test.b1.p=2; //fails
    > //defparam /tb/uut.test.b1.p=2; //fails
    > //defparam /tb/uut/test.b1.p=2; //fails
    > endmodule
    >
    >
    > If I just load the verilog module it works fine (using Modelsim):
    >
    > vlog test.v
    > vsim -c test annotate
    > examine sim:/test/b1/p -> p=2!
    >
    > Instantiating the Verilog test module in a VHDL testbench is no problem,
    > however, how to update the parameter 'p'?
    >
    > If I use:
    >
    > vlog test.v
    > vcom tb.vhd
    > vsim -c tb annotate
    >
    > I get: * Error: (vsim-3043) test.v(12): Unresolved reference to 'test' in
    > test.b1.p.
    >
    >
    > I then tried several defparam permutations all without any luck. If you

    take
    > out the annotate module the simulation runs fine but with p=1.
    >
    > I suspect that you can not reference a parameter through a VHDL entity but

    I
    > just want to make sure that is the case,
    >
    > Thanks,
    > Hans.
    >
    >
     
    Hans, Jul 29, 2004
    #2
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