need help cascading 3 decoders/counters. weird count sequence

Discussion in 'VHDL' started by k2in5, Oct 6, 2006.

  1. k2in5

    k2in5

    Joined:
    Oct 6, 2006
    Messages:
    1
    need help cascading 3 decoders/counters.

    I am using 3 * gal22v20's cant change them.
    Clocks are all wired together and ripple out is connected to the enable of the next chip. After compiling the code the MSD decoder does not count correctly and appears to be taking 9/10 clk pluses to the enable causing it to run the fast. here is the original code there are no PCB error

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;

    entity segment_cnt is

    port(

    clk,mr,en,pause, clk_in :in std_logic;
    segs :buffer std_logic_vector(6 downto 0);
    clk_out :eek:ut std_logic;
    rco : out std_logic
    );

    end segment_cnt;

    architecture behav of segment_cnt is
    begin

    cnt_proc:process(clk, mr)
    begin
    if(mr='0') then segs <= "0000001";
    elsif(clk'event and clk ='1') then
    if (pause = '0') then segs <= segs;
    elsif(en = '0' and pause = '1') then case segs is
    when "0000001" => -- 0 goto 1
    segs<="1001111";

    when "1001111" => -- 1 goto 2
    segs<="0010010";

    when "0010010" => -- 2 goto 3
    segs<="0000110";

    when "0000110"=> -- 3 goto 4
    segs<="1001100";

    when "1001100" => -- 4 goto 5
    segs<="0100100";

    when "0100100" => -- 5 goto 6
    segs<="0100000";

    when "0100000" => -- 6 goto 7
    segs<="0001111";

    when "0000111" => -- 7 goto 8
    segs<="0000000";

    when "0000000" => -- 8 goto 9
    segs<="0001100";

    when others => -- 9 goto 0
    segs<="0000001";

    end case;
    end if;
    end if;
    end process cnt_proc;
    clk_out <= clk_in;
    rco <= '1'when (segs = "0001100" and en ='0')else '0';
    end behav;


    I have tried to add a loop in the VHDL to loop 10 time before the count starts
    here is that code and the error that it produced.
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;

    entity segment_cnt is

    port(

    clk,mr,en,pause, clk_in :in std_logic;
    segs :buffer std_logic_vector(6 downto 0);
    count :buffer std_logic_vector(3 downto 0);
    clk_out :eek:ut std_logic;
    rco : out std_logic
    );

    end segment_cnt;

    architecture behav of segment_cnt is
    begin

    cnt_proc:process(clk, mr)
    begin
    if(mr='0') then segs <= "0000001";
    elsif(clk'event and clk ='1') then
    if (pause = '0') then segs <= segs;
    elsif(en = '0' and pause = '1') then

    count <= count +1;
    if (count ="1001") then
    count <= "0000";
    else count <= "0000";
    end if;
    end if;
    if(count = "1001" and pause = '1') then case segs is
    when "0000001" => -- 0 goto 1
    segs<="1001111";

    when "1001111" => -- 1 goto 2
    segs<="0010010";

    when "0010010" => -- 2 goto 3
    segs<="0000110";

    when "0000110"=> -- 3 goto 4
    segs<="1001100";

    when "1001100" => -- 4 goto 5
    segs<="0100100";

    when "0100100" => -- 5 goto 6
    segs<="0100000";

    when "0100000" => -- 6 goto 7
    segs<="0001111";

    when "0000111" => -- 7 goto 8
    segs<="0000000";

    when "0000000" => -- 8 goto 9
    segs<="0001100";

    when others => -- 9 goto 0
    segs<="0000001";

    end case;
    end if;end if;
    end process cnt_proc;
    clk_out <= clk_in;
    rco <= '1'when (segs = "0001100" and en ='0')else '0';
    end behav;

    Design optimization (dsgnopt)
    Device fitting (pla2jed)
    Error: Logic equation for signal count(3).AR is redefining a banked expression.
    Error: Logic equation for signal count(2).AR is redefining a banked expression.
    Error: Logic equation for signal count(1).AR is redefining a banked expression.
    Error: Logic equation for signal count(0).AR is redefining a banked expression.
    k2in5, Oct 6, 2006
    #1
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