POST PLACE and ROUTE SIMULATION

Discussion in 'VHDL' started by Bar Nash, Oct 6, 2008.

  1. Bar Nash

    Bar Nash Guest

    Hi all

    Do we need to do POST Place and Route simulation to verify the asic before
    production ?

    How is it done ?

    Thanks
    EC
    Bar Nash, Oct 6, 2008
    #1
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  2. Bar Nash wrote:

    > Do we need to do POST Place and Route simulation to verify the asic before
    > production ?


    This is one of many check-off items.
    Check with your asic vendor.

    > How is it done ?


    The testbench is applied to a delay-annotated
    technology netlist instead of the source code.

    -- Mike Treseler
    Mike Treseler, Oct 6, 2008
    #2
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  3. Bar Nash wrote:

    > Do we need to do POST Place and Route simulation to verify the asic before
    > production ?


    Usually you need back annotated simulations. STA is used for most of the
    timing checking, but few gate level simulations can tell if there were
    some errors in the STA setup, or some test logic/clocking structures are
    inserted incorrectly.

    Usually ASIC flows also require post p&r simulations for all the test
    vectors. The vendor will not manufacture the chip if the test vectors
    are not good enough.

    > How is it done ?


    Use the testbench, include the netlist, backannotate the sdf, add delays
    to external connections, chase all X propagations away, simulate, figure
    out why there are warnings etc. Especially the X-hunting can be very
    challenging in some designs.

    This is something that will fail almost certainly if you don't have
    access to someone who has done this before. Getting gate level
    simulations up on a asic is a huge task, and requires good knowledge
    of the design, ability to read schematics, familiarity with timing
    and the simulator. It's quite normal to find at least one bug somewhere
    in the simulator during the simulations :)

    Fortunately I'm not the one paying your NRE, if you are asking how asic
    should be verified at the late stages of the flow.

    --Kim
    Kim Enkovaara, Oct 6, 2008
    #3
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