Problem with Clock signals generated by combinational logic

Discussion in 'VHDL' started by GuitarNerd, May 17, 2005.

  1. GuitarNerd

    GuitarNerd Guest

    Hi guys/gals, im building a network interface in vhdl and trying to
    synthesize it to a XILINX Spartan-3 but im getting error messages on
    timing which looks like this:

    These 38 clock signal(s) are generated by combinatorial logic,
    and XST is not able to identify which are the primary clock signals.
    Please use the CLOCK_SIGNAL constraint to specify the clock signal(s)
    generated by combinatorial logic.

    Does anyone know how to set the Clock_signal constraint? A collegue
    suggested that maybe the problem is that alot of my design uses Mealy
    state machines which might work better in a Moore design.

    Any help is appreciated Thanks in advance

    Eric
     
    GuitarNerd, May 17, 2005
    #1
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  2. GuitarNerd

    Neo Guest

    Mealy or Moore it dosent matter, but why do you have 38 clock type
    signals in your design?
    cant say much just from the error message? atleast put the part of code
    thats being pointed out.
     
    Neo, May 17, 2005
    #2
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  3. GuitarNerd

    GuitarNerd Guest

    its a large construction with fifos and several components etc ... and
    alot of handshacking, all these handshacking signals are confusing the
    synthesizer from knowing which is the clk signal. Ive found the page
    on XILINX which says how to use the constraints, i will try it later on
    today. Thanks for your reply.

    GuitarNerd
     
    GuitarNerd, May 17, 2005
    #3
  4. GuitarNerd

    GuitarNerd Guest

    Ok im trying to use these attribute specifications but im not using
    them right since it complaining.

    attribute clock_signal : string ;
    attribute clock_signal of Clk : signal is "?????";

    Clk is the name of my clock signal......im not sure what value it
    should be passed

    GuitarNerd
     
    GuitarNerd, May 17, 2005
    #4
  5. GuitarNerd

    GuitarNerd Guest

    ok it synthesises now but no difference in the warnings

    this is what i added into the architecture:

    attribute clock_signal : string ;
    attribute clock_signal of Clk : signal is "yes";
    attribute clock_signal of c_reset : signal is "no";
    attribute clock_signal of rodata_read : signal is "no";
    attribute clock_signal of mux1_wr_en : signal is "no";
    attribute clock_signal of mux1_out : signal is "no";

    GuitarNerd
     
    GuitarNerd, May 17, 2005
    #5
  6. GuitarNerd

    Andy Peters Guest

    GuitarNerd wrote:
    > Hi guys/gals, im building a network interface in vhdl and trying to
    > synthesize it to a XILINX Spartan-3 but im getting error messages on
    > timing which looks like this:
    >
    > These 38 clock signal(s) are generated by combinatorial logic,
    > and XST is not able to identify which are the primary clock signals.
    > Please use the CLOCK_SIGNAL constraint to specify the clock signal(s)
    > generated by combinatorial logic.
    >
    > Does anyone know how to set the Clock_signal constraint? A collegue
    > suggested that maybe the problem is that alot of my design uses Mealy
    > state machines which might work better in a Moore design.


    Forget the clock constraint.

    Sounds like your design doesn't have a synchronous process! You should
    post a relevant code snippet, but my guess is your state machine
    doesn't have proper synchronous state-register update logic.

    -a
     
    Andy Peters, May 17, 2005
    #6
  7. GuitarNerd

    GuitarNerd Guest

    ok heres is one of the components. It just takes an input from one of
    two inputs and places it into a fifo. I get the following warnings when
    synthesising it:

    rnitop_rni_downstream_Mux1__n0030(rnitop_rni_downstream_Mux1__n0030:O)|
    NONE(*)(rnitop_rni_downstream_Mux1_muwr_ack)| 1 |
    rnitop_rni_downstream_Mux1__n0031(rnitop_rni_downstream_Mux1__n0031:O)|
    NONE(*)(rnitop_rni_downstream_Mux1_vcwr_ack)| 1 |
    rnitop_rni_downstream_Mux1_State_FFd5:Q| NONE | 1
    |
    rnitop_rni_downstream_Mux1__n0032(rnitop_rni_downstream_Mux1__n0032:O)|
    NONE(*)(rnitop_rni_downstream_Mux1_fdata_106)| 121 |

    Code:

    library ieee;
    use ieee.std_logic_1164.all;

    entity mux1_downstream is

    port (
    Clk,Reset : in std_logic;
    --to vc_downstream
    vcdata : in std_logic_vector(127 downto 0);
    vcwr_ack : out std_logic;
    vcwr_en : in std_logic;
    --to FIFO2_downstream
    fdata : out std_logic_vector(127 downto 0);
    fwr_en : out std_logic;
    fwr_ack : in std_logic;
    --to mux1_uppstream
    mudata : in std_logic_vector(127 downto 0);
    muwr_ack : out std_logic;
    muwr_en : in std_logic);

    end mux1_downstream;

    architecture Arch_mux1_downstream of mux1_downstream is

    type State_type is (SInit,S0,S1,S1_1,S2,S2_1,S3);
    signal State : State_type := SInit;
    signal Next_state : State_type := SInit;

    begin

    Clock: process (Clk,Reset, Next_state)

    begin

    if Reset = '0' then
    State <= SInit;
    elsif Clk = '1' and Clk'event then
    State <= Next_state;
    end if;

    end process;


    transition: process(State, vcwr_en, vcdata, mudata, muwr_en, fwr_ack)
    begin
    case State is

    when SInit =>

    fdata <= (others => '0');
    fwr_en <= '0';
    vcwr_ack <= '0';
    muwr_ack <= '0';
    Next_state <= S0;


    --------------------------------------------------------------------------------------------------------


    when S0 =>

    if muwr_en = '1' then
    fdata <= mudata;
    Next_state <= S1;
    elsif vcwr_en = '1' then
    fdata <= vcdata;
    Next_state <= S2;
    else
    Next_state <= S0;
    end if;


    --------------------------------------------------------------------------------------------------------
    --for mux
    when S1 =>

    fwr_en <= '1';
    Next_state <= S1_1;

    when S1_1 =>

    if fwr_ack = '1' then
    fwr_en <= '0';
    muwr_ack <= '1';
    Next_state <= SInit;
    else
    Next_state <= S1_1;
    end if;


    -------------------------------------------------------------------------------------------------------
    --for vc
    when S2 =>

    fwr_en <= '1';
    Next_state <= S2_1;

    when S2_1 =>

    if fwr_ack = '1' then
    fwr_en <= '0';
    vcwr_ack <= '1';
    Next_state <= SInit;
    else
    Next_state <= S2_1;
    end if;


    --------------------------------------------------------------------------------------------------------



    when others =>
    fdata <= (others => '0');
    fwr_en <= '0';
    vcwr_ack <= '0';
    muwr_ack <= '0';
    end case;
    end process;
    end Arch_mux1_downstream;
     
    GuitarNerd, May 18, 2005
    #7
  8. GuitarNerd

    Neo Guest

    One problem I see in this is that you are not assigning to the outputs
    in the else clauses inside the transition process and also you need to
    have assignments to all outputs in each state.
     
    Neo, May 19, 2005
    #8
  9. GuitarNerd

    Andy Peters Guest

    Neo wrote:
    > One problem I see in this is that you are not assigning to the

    outputs
    > in the else clauses inside the transition process and also you need

    to
    > have assignments to all outputs in each state.


    This is the best argument in favor of single-(clocked)process state
    machines.

    -a
     
    Andy Peters, May 19, 2005
    #9
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