Quartus II v5.1 don't read a file

[ontos]

Hi, for all. I'm using Altera software - Quartus II v 5.1 and i have a problem with reading text file. My code is below:
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_textio.all;
USE std.TEXTIO.ALL;
ENTITY files IS
PORT( go : IN std_logic);
END files;
ARCHITECTURE simple OF files IS
BEGIN
PROCESS(go)
FILE infile : TEXT IS IN "C:\infile.txt";
FILE outfile : TEXT IS OUT "C:\outfile.txt";
VARIABLE out_line, my_line : LINE;
VARIABLE int_val : INTEGER;
BEGIN
WHILE NOT( ENDFILE(infile)) LOOP
-- read a line from the input file
READLINE( infile, my_line);
-- read a value from the line
READ( my_line, int_val);
-- square the value
int_val := int_val **2;
-- write the squared value to the line
WRITE( out_line, int_val);
-- write the line to the output file
WRITELINE( outfile, out_line);
END LOOP;
END PROCESS;
END simple;

First when i'm using use ieee.std_logic_textio.all package, Quartus show this error:

Error (10481): VHDL Use Clause error at files.vhd(3): design library "ieee" does not contain primary unit "std_logic_textio"

second, when i dont use this package, Quartus say:
Error (10536): VHDL Loop Statement error at files.vhd(16): loop must terminate at or before 10000 iterations

Could you help me?
Thank you

 

[picnanard]

answer

Hi, for all. I'm using Altera software - Quartus II v 5.1 and i have a problem with reading text file. My code is below:
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_textio.all;
USE std.TEXTIO.ALL;
ENTITY files IS
PORT( go : IN std_logic);
END files;
ARCHITECTURE simple OF files IS
BEGIN
PROCESS(go)
FILE infile : TEXT IS IN "C:\infile.txt";
FILE outfile : TEXT IS OUT "C:\outfile.txt";
VARIABLE out_line, my_line : LINE;
VARIABLE int_val : INTEGER;
BEGIN
WHILE NOT( ENDFILE(infile)) LOOP
-- read a line from the input file
READLINE( infile, my_line);
-- read a value from the line
READ( my_line, int_val);
-- square the value
int_val := int_val **2;
-- write the squared value to the line
WRITE( out_line, int_val);
-- write the line to the output file
WRITELINE( outfile, out_line);
END LOOP;
END PROCESS;
END simple;

First when i'm using use ieee.std_logic_textio.all package, Quartus show this error:

Error (10481): VHDL Use Clause error at files.vhd(3): design library "ieee" does not contain primary unit "std_logic_textio"

second, when i dont use this package, Quartus say:
Error (10536): VHDL Loop Statement error at files.vhd(16): loop must terminate at or before 10000 iterations

Could you help me?
Thank you

I have the same problem the last week
This file is a bench file for read or write simulate file.
You must be to aime this file in tools-simulate-testbench
This bench file must not appear in project file remove it.
Quartus compile all project file without bench file.
when start stimulation modelsim compile all with bench

 

[ontos]

But in my Project is only one file: Procect -> Settings->Files and i see only files.vhd. Section User Libraries (Current Procect) is empty. What exactly mus i do to avoid error?

 

[picnanard]

answer

But in my Project is only one file: Procect -> Settings->Files and i see only files.vhd. Section User Libraries (Current Procect) is empty. What exactly mus i do to avoid error?

Yes if your file appear in project-settings-file, this file belong project.

 

[ontos]

And so? i know that tiles.vhd belong project, but wherewith involved is package std_logic_textio with Project -> Files...?
And why is error about loop iteration?

I have include other package from dir ../libararys/vhdl/ (libarary altera; use.altera. ... and the like)- all is ok, but one package std_logic_textio have problem...
Help me please.
Thank You!

 

[picnanard]

answer

And so? i know that tiles.vhd belong project, but wherewith involved is package std_logic_textio with Project -> Files...?
And why is error about loop iteration?

I have include other package from dir ../libararys/vhdl/ (libarary altera; use.altera. ... and the like)- all is ok, but one package std_logic_textio have problem...
Help me please.
Thank You!

Excuse me for this delay.
You use std_logic_textio in vhdl bench file
and this file bench must no appear in project file.
You must be place this file bench in assignement setting simualtion in quartus.
I hope to be clear

 

[ontos]

So, I have made all. I have copy SYN_TEXTIO.VHD file in Project dir, and include it in Assigments-> Settings->Files. Now there are 4 files: SYN_TEXTIO.VHD, C:/outfile.txt, C:/infile.txt and files.vhd.
But by Synthesis i have this error:

Error (10536): VHDL Loop Statement error at files.vhd(16): loop must terminate at or before 10000 iterations