ram

[AMARO]

Hi,

I'm trying to build a VHDL code for a RAM model with two address
decoders,
One is the row decoder and the second is column decoder
these decoders select a single cell (1-bit) during read or write
operation.

unfortunately most of the VHDL books and even the internet describe
only a single type of memory that comes with 8 bits wide data bus.

and declared like this
data : in std_logic_vector (7 downto 0);

I'm very keen to know how it can be modelled

could you please give me an answer to my questions



Cheers
allan martin

 

[Tricky]

Hi,

I'm trying to build a VHDL code for a RAM model with two address
decoders,
One is the  row decoder and the second is column decoder
these decoders  select a single cell (1-bit) during read or write
operation.

unfortunately most of the VHDL books and even the internet describe
only a single type of memory that comes with  8 bits wide data bus.

and declared like this
data : in std_logic_vector (7 downto 0);

I'm very keen to know how it can be modelled

could you please give me an answer to my questions

Cheers
allan martin

How is it any different? surely if you have a row and column address
you end up with a single data value in the end?
And row and column architecutre can still be a 1D array, with one of
row/column being the MSBs and the other being the LSBs of the address
bus.

 

[Rick]

There are a number of x1 memories in the gnrcsram library on the FMF
website (http://www.FreeModelFoundry.com). They are not synthesizable
but you did not ask for that.

Rick