Req.: Timing reports from various tools

Discussion in 'VHDL' started by acd, Mar 29, 2006.

  1. acd

    acd Guest

    I am going to supervise a Bachalor thesis which requires processing
    timing report files.
    I would like to make it as tool independent as possible.
    I have access to Xilinx- and Altera-tools on the FPGA side and
    Booledozer (IBM internal tool).
    I would also like to incorporate report files from Synopsys and
    Cadence,
    and maybe other, if I can get a hand on it.

    The design is not that much important, any open core or similar will
    do,
    and it should contain at least 100 pathes.

    If someone could help me on this, I would be very grateful.
    (And it would result in the tool beeing mentioned in the thesis, and
    hopefully
    related publications).
    So, dear FAEs please sit down, look at your favourate demo and send me
    the report.

    Thank you in advance,

    Andreas
     
    acd, Mar 29, 2006
    #1
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