setup vs. clock-to-output time vs. hold time

Discussion in 'VHDL' started by Bochumfrau@gmx.de, May 13, 2004.

  1. Guest

    Hello,

    I am new to VHDL and FPGA design.

    My question:

    I want to make a synchronous design.

    What is the condition for a synchronous design to work
    with regard to the setup and clock-to-output and hold time of
    the FFs?

    Does the setup time have to be smaller than the clock-to-output
    time?
    What about the hold time in respect to setup and clock-to-output?


    Thanks to you.

    Rgds
     
    , May 13, 2004
    #1
    1. Advertising

  2. Ray Andraka Guest

    Set up time is the amount of time before the clock edge that the
    input signal needs to be stable to guarantee it is accepted properly
    on the clock edge. Hold time is the amount of time after the clock
    edge that same input signal has to be held before changing it to make
    sure it is sensed properly at the clock edge. The clock to output
    time is the worst case time it takes for a signal to propagate out
    after the clock edge.

    Now that you know that, it is fairly easy to see that the clock to
    output time plus signal propagation time on the route to the other
    flip-flop plus the set up time must be less than the period of the
    clock. Tco + Tpd + Tsu < Tclk

    To satisfy hold time, the clock to output time plus the propagation
    delay must be greater than the hold time. Chip makers try to make
    the hold times negative because it is hard to guarantee minimum
    propagation times.


    "" wrote:

    > Hello,
    >
    > I am new to VHDL and FPGA design.
    >
    > My question:
    >
    > I want to make a synchronous design.
    >
    > What is the condition for a synchronous design to work
    > with regard to the setup and clock-to-output and hold time of
    > the FFs?
    >
    > Does the setup time have to be smaller than the clock-to-output
    > time?
    > What about the hold time in respect to setup and clock-to-output?
    >
    > Thanks to you.
    >
    > Rgds


    --
    --Ray Andraka, P.E.
    President, the Andraka Consulting Group, Inc.
    401/884-7930 Fax 401/884-7950
    email
    http://www.andraka.com

    "They that give up essential liberty to obtain a little
    temporary safety deserve neither liberty nor safety."
    -Benjamin Franklin, 1759
     
    Ray Andraka, May 13, 2004
    #2
    1. Advertising

  3. <> wrote in message
    news:...
    > Hello,
    >
    > I am new to VHDL and FPGA design.
    >
    > My question:
    >
    > I want to make a synchronous design.
    >
    > What is the condition for a synchronous design to work
    > with regard to the setup and clock-to-output and hold time of
    > the FFs?
    >
    > Does the setup time have to be smaller than the clock-to-output
    > time?
    > What about the hold time in respect to setup and clock-to-output?
    >
    >
    > Thanks to you.
    >
    > Rgds

    I'm not sure what you mean my "clock-to-output" time. Latch clock input
    pin to latch output pin?

    Anyway, for a synchronous design to work the worst-case latch-to-latch
    path delays must be less than (clock period - latch setup requirement).
    The latch-to-latch path delays include the delay through a latch (clock
    input to latch output) and all the delays through the combinational
    logic feeding the next latch, including the delays through the gates
    themselves and the delays through the wires connecting them.

    Also, the best-case latch-to-latch delay must be greater than the latch
    hold time requirement.

    In addition, the primary input to latch setup and hold times must be met
    as well as the required arrival times at the primary outputs.

    Skew in the clock tree also needs to be considered.
     
    Charles Bailey, May 13, 2004
    #3
  4. Bochumfrau wrote:
    > I want to make a synchronous design.


    Excellent choice.

    > What is the condition for a synchronous design to work
    > with regard to the setup and clock-to-output and hold time of
    > the FFs?


    1. All inputs are synchronized to the system clock.
    2. There is only one system clock. Any other inputs
    that "feel" like clocks are synchronized and become
    regular inputs or synchronous clock enables.
    3. The VHDL code uses the synchronous template for all processes.
    4. Constrain the place+route reg to reg fmax to sys_clk
    5. Verify that fmax has been met by the static timer.

    That's it. The computer will worry about the setup/hold requirements
    to meet fmax. You don't need any other constraints.

    -- Mike Treseler
     
    Mike Treseler, May 13, 2004
    #4
  5. Ken Guest

    > To satisfy hold time, the clock to output time plus the propagation
    > delay must be greater than the hold time. Chip makers try to make
    > the hold times negative because it is hard to guarantee minimum
    > propagation times.


    Negative hold time? What does that mean?

    Ken
     
    Ken, May 14, 2004
    #5
  6. Ken a écrit:
    >>To satisfy hold time, the clock to output time plus the propagation
    >>delay must be greater than the hold time. Chip makers try to make
    >>the hold times negative because it is hard to guarantee minimum
    >>propagation times.

    >
    > Negative hold time? What does that mean?


    The value on the input can change *before* the clock edge and still be
    carried to the output.

    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
     
    Nicolas Matringe, May 14, 2004
    #6
  7. Ray Andraka Guest

    it means that the window in which the input signal has to be held stable
    ends before the arrival of the clock edge. This happens if the
    propagation delay on the data path is guaranteed to be longer than the
    propagation of the clock to the same flip-flop. It is far easier to
    guarantee relative delays on a monolithic chip than it is to guarantee
    minimum delays at the board level where you have different chips. For
    that reason, it is desirable for the chip manufacturers to make the hold
    times zero or negative by careful use of delays. On the other hand,
    adding delays to get a zero or negative hold time degrades maximum
    performance, so if the component is one that is used in an application
    where they know you will have some minimum clock to out delay (or think
    you will anyway), it is common to have a positive hold time. An example
    of that is memories.

    Ken wrote:

    >
    > Negative hold time? What does that mean?
    >
    > Ken


    --
    --Ray Andraka, P.E.
    President, the Andraka Consulting Group, Inc.
    401/884-7930 Fax 401/884-7950
    email
    http://www.andraka.com

    "They that give up essential liberty to obtain a little
    temporary safety deserve neither liberty nor safety."
    -Benjamin Franklin, 1759
     
    Ray Andraka, May 14, 2004
    #7
  8. Guest

    Thank you very much for your answers : )
     
    , May 17, 2004
    #8
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. prem_eda
    Replies:
    5
    Views:
    8,034
    Pieter Hulshoff
    Oct 11, 2004
  2. =?iso-8859-1?q?Guilherme_Corr=EAa?=

    "signal does not hold its value outside clock edge"

    =?iso-8859-1?q?Guilherme_Corr=EAa?=, Jan 23, 2006, in forum: VHDL
    Replies:
    5
    Views:
    6,183
    =?iso-8859-1?q?Guilherme_Corr=EAa?=
    Jan 23, 2006
  3. maazbecin

    why "setup-time and hold-time"?

    maazbecin, Jul 24, 2006, in forum: VHDL
    Replies:
    0
    Views:
    3,214
    maazbecin
    Jul 24, 2006
  4. mayurvlsi

    Setup n hold time

    mayurvlsi, Jul 13, 2007, in forum: VHDL
    Replies:
    0
    Views:
    610
    mayurvlsi
    Jul 13, 2007
  5. Trygve Laugstøl
    Replies:
    4
    Views:
    4,567
    rickman
    Jan 24, 2011
Loading...

Share This Page