Shift right : does not compile in Modelsim VCOM

Discussion in 'VHDL' started by Pasacco, Sep 8, 2007.

  1. Pasacco

    Pasacco Guest

    In VHDL code, following libraries and signals are defined.
    -------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    use IEEE.NUMERIC_STD.ALL;
    .....
    signal HF : std_logic_vector(15 downto 0);
    signal LF : std_logic_vector(15 downto 0);
    -------------------

    Problem is that

    Following "shift right" is not working.
    --------------------
    HF <= LF srl 2; -- logical shift right
    --------------------

    Modelsim 6.1c reports following error :
    -------------------
    # ** Error: HF.vhd(113): No feasible entries for infix operator "srl".
    # ** Error: HF.vhd(113): Type error resolving infix expression "srl"
    as type std_logic_vector.
    -------------------

    I tried different ways, such as "SHR, SHIFT_RIGHT" with different data
    types.

    If anyone had same problem, please let me know how to resolve this
    problem.
    thank you in advance
    Pasacco, Sep 8, 2007
    #1
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  2. Pasacco

    Duane Clark Guest

    Pasacco wrote:
    > In VHDL code, following libraries and signals are defined.
    > -------------------
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    > use IEEE.NUMERIC_STD.ALL;


    Don't mix NUMERIC_STD with STD_LOGIC_ARITH/STD_LOGIC_UNSIGNED. In fact,
    you really should not be using STD_LOGIC_ARITH/STD_LOGIC_UNSIGNED at
    all, ever.

    > ....
    > signal HF : std_logic_vector(15 downto 0);
    > signal LF : std_logic_vector(15 downto 0);
    > -------------------
    >
    > Problem is that
    >
    > Following "shift right" is not working.
    > --------------------
    > HF <= LF srl 2; -- logical shift right
    > --------------------


    I don't really see a reason to bother with srl and similar operators for
    that.

    HF <= LF(1 downto 0) & LF(15 downto 2);
    Duane Clark, Sep 8, 2007
    #2
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  3. On Sat, 08 Sep 2007 09:17:48 -0700, Pasacco <> wrote:

    >In VHDL code, following libraries and signals are defined.
    >-------------------
    >library IEEE;
    >use IEEE.STD_LOGIC_1164.ALL;
    >use IEEE.STD_LOGIC_ARITH.ALL;
    >use IEEE.STD_LOGIC_UNSIGNED.ALL;
    >use IEEE.NUMERIC_STD.ALL;


    As Duane already said, this is a total mess;
    STD_LOGIC_ARITH and NUMERIC_STD both define
    a bunch of things with the same names, and
    the two USE clauses render *both* sets of
    definitions invisible. However, that's not
    the problem here.

    >signal HF : std_logic_vector(15 downto 0);
    >signal LF : std_logic_vector(15 downto 0);
    >...
    >HF <= LF srl 2; -- logical shift right


    ># ** Error: HF.vhd(113): No feasible entries for infix operator "srl".


    Indeed so. The shift operators have no implicit (built-in)
    definition, and std_logic_1164 does not provide definitions
    for them.

    You can sooooo easily define your own - details below - but
    you can also use the shift operators defined on UNSIGNED
    vectors in NUMERIC_STD (if, of course, you get rid of the
    conflicting USE clause for STD_LOGIC_ARITH).

    HF <= std_logic_vector( unsigned(LF) srl 2 );

    Yes, I know it's ugly. So, why not make your own?

    function "srl" (L: std_logic_vector; R: natural)
    return std_logic_vector is
    variable V: std_logic_vector(L'length-1 downto 0);
    begin
    if R >= L'length then
    V := (others => '0');
    else
    V := L;
    end if;
    for i in V'range loop
    if i < R then
    V(i) := '0';
    else
    V(i) := V(i-R);
    end if;
    end loop;
    return V;
    end;

    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Sep 8, 2007
    #3
  4. On Sat, 08 Sep 2007 19:51:15 +0100, Jonathan Bromley
    <> wrote:

    >You can sooooo easily define your own [srl operator]


    ahem, yes, but the code I provided does a LEFT shift :)
    whoops, sorry. It is left as a trivial exercise for the
    reader to rewrite it to do RIGHT shift as required!
    (hint: make sure you iterate over the vector elements
    in the correct order... and don't be frightened of
    giving the internal variable a different declaration
    if it makes life easier).
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Sep 8, 2007
    #4
  5. Pasacco

    Pasacco Guest

    Now it compiles. Thank you for providing 3 solutions.
    Pasacco, Sep 9, 2007
    #5
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