simulation error

Discussion in 'VHDL' started by u_stadler@yahoo.de, Oct 2, 2005.

  1. Guest

    , Oct 2, 2005
    #1
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  2. Guest

    on thing i forgot to ask:

    when i synthesise the design it assumes that thr RD and WR signals are
    clocks. how can i avoid this? is there a command?. the reason why i
    don't want this is because when i want to assign package pins i will
    only allow me to use clock pins for those signals.

    thanks
    , Oct 2, 2005
    #2
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  3. wrote:

    > any ideas why? or is this design in general bad?


    The design lacks a clock input and
    instead uses WR and RD as clocks.

    -- Mike Treseler
    Mike Treseler, Oct 2, 2005
    #3
  4. wrote:

    > when i synthesise the design it assumes that thr RD and WR signals are
    > clocks. how can i avoid this?


    Add a clock input and use 'event with no other inputs.

    -- Mike Treseler
    ____________________________
    IN_SYNC: process(RESET, clk)
    begin
    if RESET = '0' then
    s_In_Data <= (others => '0');
    elsif rising_edge(clk) then
    if WR = '1' then
    s_In_Data <= s_Next_In_Data;
    s_In_Count <= s_Next_In_Count;
    end if;
    end if;
    end process IN_SYNC;
    Mike Treseler, Oct 2, 2005
    #4
  5. Guest

    but how can i trigger on a rising edge then?
    for example i only want to copy the input on the rising edge of WR?
    , Oct 2, 2005
    #5
  6. wrote:
    > but how can i trigger on a rising edge then?


    make a synchronous strobe using an
    AND gate, inverter and one flop.

    > for example i only want to copy the input on the rising edge of WR?


    Use the strobe in the clocked process:

    if strobe = '1' then
    some_reg <= input_to_copy;
    end if;

    Here's a related example of counting rising edges
    using a synchronous strobe:

    http://home.comcast.net/~mike_treseler/rise_count.vhd

    This uses variables instead of signals,
    but it's the same idea.

    -- Mike Treseler
    Mike Treseler, Oct 2, 2005
    #6
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