Simulation is OK but problem with synthesis

[Andy]

Hi,
I wrote a FSM to control the operation of my hardware. In this FSM I
set some load signals. As I mentioned the simulation works, but when I
try to synthesize my design with the XST the error message "Signal
load<0> cannot be synthesized, bad synchronous description." appears.
So if someone could tell me what is meant by this error message or
could give me a hint where I could find a more detailed error
description I would be very thankfull.

best regards,
Andreas

 

[Jan De Ceuster]

Hi,

I wrote a FSM to control the operation of my hardware. In this FSM I
set some load signals. As I mentioned the simulation works, but when I
try to synthesize my design with the XST the error message "Signal
load<0> cannot be synthesized, bad synchronous description." appears.
So if someone could tell me what is meant by this error message or
could give me a hint where I could find a more detailed error
description I would be very thankfull.

best regards,
Andreas

Hi Andres,

can you give some code of what you have done? It's a bit hard to debug
without any information.

kind regards,
Jan

 

[Andy]

Hi Andres,

can you give some code of what you have done? It's a bit hard to debug
without any information.

kind regards,
Jan

Hi Jan,

thanx for your help in advance,

it's just a simple one-hot encoded FSM, where I set some control
signals for my datapath logic amongst which are load signals for all
my accumulator units; these load signals are set to zero in all the
states except in states S_SHIFT_REG_LOADING and S_RUN_MATCHING where I
set one load signal to 1

one thing I tried was to comment out the errornous lines but then the
same problem arose with the signal "en_x_pos_count";

kind regards,
Andreas

-- code

Generic(
accu_count: integer := 468
);

....
signal load: std_logic_vector(accu_count-1 downto 0);
....



....
next_state_and_output: process(current_state, sr_full, start_matching,
line_finished, internal_x_position, image_line_finished)
begin
case current_state is
when S_RESET =>

for index in 0 to accu_count-1 loop
load(index) <= '0';
end loop;
clr_x_counter <= '0';
clr_accu <= '0';
load_template <= '0';
clr_line_counter <= '1';
en_matching <= '0';
en_line_counter <= '0';
clr_template_reg <= '0';
en_x_pos_count <= '0';
load_shift_reg <= '0';
clr_shift_reg <= '0';

next_state <= S_IDLE;

...

when S_SHIFT_REG_LOADING =>

for index in 0 to accu_count-1 loop
load(index) <= '0';
end loop;
load_template <= '1';
en_line_counter <= '0';
clr_x_counter <= '0';
clr_shift_reg <= '0';
load_shift_reg <= '1';

if sr_full'event and sr_full = '1' then
next_state <= S_RUN_MATCHING;
load(conv_integer(internal_x_position)) <= '1';
en_x_pos_count <= '1';
else
en_x_pos_count <= '0';
next_state <= S_SHIFT_REG_LOADING;
end if;
...

when S_RUN_MATCHING =>

for index in 0 to accu_count-1 loop
load(index) <= '0';
end loop;
load_template <= '0';
clr_x_counter <= '0';
load_shift_reg <= '1';
if image_line_finished = '1' then
next_state <= S_IDLE;
elsif image_line_finished = '0' then

if line_finished = '1' then
en_x_pos_count <= '0';
next_state <= S_NEXT_TEMPLATE_LINE;
elsif line_finished = '0' then

load(conv_integer(internal_x_position)) <= '1';
en_x_pos_count <= '1';
next_state <= S_RUN_MATCHING;
end if;
end if;
...

 

[Ralf Hildebrandt]

"Andy"



This is something like a double-edge triggered flipflop or an
edge-triggered piece of code within a case-statement.


...

begin
case current_state is ....
when S_SHIFT_REG_LOADING => ....
if sr_full'event and sr_full = '1' then

And there this error could be found. Always use the following template
for flipflops:

process(asyn_reset,clock)
begin
if (asyn_reset='1') then
-- do some reset
elsif rising_edge(clock) then
-- do some other logic stuff (loop, case, if...)
end if;
end process;


Ralf

 

[Jan De Ceuster]

Hi,

Hi Jan,

thanx for your help in advance,

it's just a simple one-hot encoded FSM, where I set some control
signals for my datapath logic amongst which are load signals for all
my accumulator units; these load signals are set to zero in all the
states except in states S_SHIFT_REG_LOADING and S_RUN_MATCHING where I
set one load signal to 1

one thing I tried was to comment out the errornous lines but then the
same problem arose with the signal "en_x_pos_count";

kind regards,
Andreas

-- code

Generic(
accu_count: integer := 468
);

...
signal load: std_logic_vector(accu_count-1 downto 0);
...



...
next_state_and_output: process(current_state, sr_full, start_matching,
line_finished, internal_x_position, image_line_finished)
begin
case current_state is
when S_RESET =>

for index in 0 to accu_count-1 loop
load(index) <= '0';
end loop;
clr_x_counter <= '0';
clr_accu <= '0';
load_template <= '0';
clr_line_counter <= '1';
en_matching <= '0';
en_line_counter <= '0';
clr_template_reg <= '0';
en_x_pos_count <= '0';
load_shift_reg <= '0';
clr_shift_reg <= '0';

next_state <= S_IDLE;

...

when S_SHIFT_REG_LOADING =>

for index in 0 to accu_count-1 loop
load(index) <= '0';
end loop;
load_template <= '1';
en_line_counter <= '0';
clr_x_counter <= '0';
clr_shift_reg <= '0';
load_shift_reg <= '1';

if sr_full'event and sr_full = '1' then
next_state <= S_RUN_MATCHING;
load(conv_integer(internal_x_position)) <= '1';
en_x_pos_count <= '1';
else
en_x_pos_count <= '0';
next_state <= S_SHIFT_REG_LOADING;
end if;
...

when S_RUN_MATCHING =>

for index in 0 to accu_count-1 loop
load(index) <= '0';
end loop;
load_template <= '0';
clr_x_counter <= '0';
load_shift_reg <= '1';
if image_line_finished = '1' then
next_state <= S_IDLE;
elsif image_line_finished = '0' then

if line_finished = '1' then
en_x_pos_count <= '0';
next_state <= S_NEXT_TEMPLATE_LINE;
elsif line_finished = '0' then

load(conv_integer(internal_x_position)) <= '1';
en_x_pos_count <= '1';
next_state <= S_RUN_MATCHING;
end if;
end if;
...

Hi Andy,

I think your problem is here:
process (bla bla bla)
....
when S_SHIFT_REG_LOADING =>
....
if sr_full'event and sr_full = '1' then
next_state <= S_RUN_MATCHING;
load(conv_integer(internal_x_position)) <= '1';
en_x_pos_count <= '1';
else
en_x_pos_count <= '0';
next_state <= S_SHIFT_REG_LOADING;
end if;
.....

For synthesis you can only use constructs like "signal'event and signal = '1'"
for synchronous behaviour. To keep it simple: you can only use 'event when you
want to describe a clocked process.

If you realy need to see a rising edge on sr_full a sollution might be to do
something like this:

process(clk)
if rising_edge(clk) then
d_sr_full <= sr_full;
end if;

rising_edge_sr_full <= '1' when sr_full = '1' and d_sr_full = '0'
else '0';

Or just
rising_edge_sr_full <= sr_full and not d_sr_full;

This creates a pulse when sr_full goes from 0 to 1. Mind that the pulse width
strongly depends on the timings of sr_full. If sr_full is an output of a
flip-flop then rising_edge_sr_full will have a pulse width of aproximatly 1
clock cycle (less than but this depends on several timing stuff).

hope this helps,

kind regards,
Jan

 

[Andy]

Good morning,

thanx for your help, I've implemented it and it's running.

As I'm a newbie to VHDL it's a little bit hard to keep in mind the
differences between simulation and synthesis.

thanx a lot,
kind regards
Andreas