simulation problem

Discussion in 'VHDL' started by Urban Stadler, Jul 24, 2004.

  1. hi

    i'm quite new to vhdl and i'm trying to simulate some code with modelsim 5.7
    the behavioral simulation works fine but when i try to simulate a post fit
    model i get the following error message:

    # -- Loading entity fgtp
    # WARNING[1]: test.vhd(67): Types do not match for port s_clock_count
    # WARNING[1]: test.vhd(67): A use of this default binding for this component
    instantiation will result in an elaboration error.
    # vsim -lib work -sdfmax /UUT=fgtp_timesim.sdf -t 1ps fgtp_test_vhd_tb

    the code around the line 67 is:

    in fgtp.vhdl

    if s_clock_count = ( (c_Clock / 2)) then
    takt <= '0';
    elsif s_clock_count = ( c_Clock - 1 ) then
    takt <= '1';
    s_clock_count <= 0;
    end if;

    the tesbenchcode around 67 is:

    UUT : fgtp
    PORT MAP (
    RESET => RESET,
    CLK => CLK,
    CLK_1MHZ => CLK_1MHZ,
    takt => takt,
    s_clock_count => s_clock_count,


    Sensor_Reset => Sensor_Reset,
    s_Sensor_Ready => s_Sensor_Ready,
    Sensor_Request => Sensor_Request
    );

    could anybody help me here please?

    thanks
    urban
    Urban Stadler, Jul 24, 2004
    #1
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  2. Urban Stadler wrote:
    > hi
    >
    > i'm quite new to vhdl and i'm trying to simulate some code with modelsim 5.7
    > the behavioral simulation works fine but when i try to simulate a post fit
    > model i get the following error message:
    >
    > # -- Loading entity fgtp
    > # WARNING[1]: test.vhd(67): Types do not match for port s_clock_count
    > # WARNING[1]: test.vhd(67): A use of this default binding for this component
    > instantiation will result in an elaboration error.
    > # vsim -lib work -sdfmax /UUT=fgtp_timesim.sdf -t 1ps fgtp_test_vhd_tb
    >
    > the code around the line 67 is:
    >
    > in fgtp.vhdl
    >
    > if s_clock_count = ( (c_Clock / 2)) then
    > takt <= '0';
    > elsif s_clock_count = ( c_Clock - 1 ) then
    > takt <= '1';
    > s_clock_count <= 0;
    > end if;
    >
    > the tesbenchcode around 67 is:
    >
    > UUT : fgtp
    > PORT MAP (
    > RESET => RESET,
    > CLK => CLK,
    > CLK_1MHZ => CLK_1MHZ,
    > takt => takt,
    > s_clock_count => s_clock_count,
    >
    >
    > Sensor_Reset => Sensor_Reset,
    > s_Sensor_Ready => s_Sensor_Ready,
    > Sensor_Request => Sensor_Request
    > );
    >
    > could anybody help me here please?


    A common reason for behavioural/post-route mismatches is that some
    synthesizers will alter the type of the port as a result of optimization.

    For instance, suppose you specify a port as an 'inout'. If the
    synthesizer determines you never read from the port, it may convert it
    to type 'out' which will cause the error you see.

    Another possibility is that the synthesizer may reverse the range of a
    port, converting a 'to' range to a 'downto' range. Check the entity of
    the post-route model carefully to make sure it still matches your
    behavioural model.
    --
    Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
    Tim Hubberstey, Jul 24, 2004
    #2
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