# space vector modulation fpga

Discussion in 'VHDL' started by hasanabouali, Nov 17, 2004.

1. ### hasanaboualiGuest

i really wanna have the code written by vhdl language implement space
vector modulation i will be very very thankfull, if u get it to me be sure
i can help u in any thing related to embeded system

hasanabouali, Nov 17, 2004

2. ### NeoGuest

Neo, Nov 18, 2004

3. ### hasanaboualiGuest

i wanna to implement space vector modulation by FPGA
then
i control the speed of an induction motor

the problem is sin & cos in fpga
i hope any one can show me the way, i hope also there is a simulation
prog. or where can i find good papers.

hasanabouali, Nov 22, 2004
4. ### NeoGuest

"hasanabouali" <> wrote in message news:<>...
> i wanna to implement space vector modulation by FPGA
> then
> i control the speed of an induction motor
>
> the problem is sin & cos in fpga
> i hope any one can show me the way, i hope also there is a simulation
> prog. or where can i find good papers.

Hi,
Its not difficult, you can do that with look up tables if the
resolution requirement is not high or best go for cordic
implementation. it will converge rapidly within a few iterations. you
can check out this document, its a good ref to cordic in fpga.
http://www.andraka.com/papers.htm

Neo, Nov 24, 2004
5. ### hasanaboualiGuest

In the name of Allah the most merciful
Thank you zingafriend very much for answering me But what I need exactly
is:
I need to read three voltages and convert them to just two this is not a
problem
But I need to take these values and implement these equation
θ=cos-1(Vα/Vβ) & ta = U[cos() –
(3-½)sin()] & tb = 2U(3-½)sin()
this is my vision, our supervisor refuse to tell us more for now.
**I noticed that in the cordic algorithm which you told me about it
doesn't contain VHDL code.
Thank you anyway if you don't have a problem to talk to me online I will
be happy for that.
Also my e-mail if you want to add me to ur
messenger. IF u have any question about power electronics don't hesitate
just tell me if I can't help u I will find someone can.
urs:hasan

hasanabouali, Nov 24, 2004
6. ### teslaGuest

> But I need to take these values and implement these equation
> θ=cos-1(Vα/Vβ) & ta = U[cos() –
> (3-½)sin()] & tb = 2U(3-½)sin()

> this is my vision, our supervisor refuse to tell us more for now.
> **I noticed that in the cordic algorithm which you told me about it
> doesn't contain VHDL code.

check

http://www.opencores.org/browse.cgi/by_category

there are some cordic implementations.

"look up table" is also a good idea.

yusuf

tesla, Nov 25, 2004
7. ### hasanaboualiGuest

dear yusuf

thank you, i realy want the vhdl code that implement sin or cosine, i
can't understand this method.
do you have solved example which already implement cosine by cordic
urs:hasan

hasanabouali, Dec 7, 2004
8. ### veiledcavalier

Joined:
Dec 12, 2008
Messages:
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0
Salam alikom dear hassanabouali,
i am a student working also with SVM and doing it on FPGA
i think we can exchange knowledge in Power Electronics and
SVM if u don't mind !

i sent u on mail. i'd be grateful if we co-operate.
thanks a lot

veiledcavalier, Dec 12, 2008
9. ### jeppe

Joined:
Mar 10, 2008
Messages:
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0
Location:
Denmark
jeppe, Dec 12, 2008
10. ### balaji

Joined:
Feb 22, 2009
Messages:
2
0
Hi friend
I just started working on the same kind of project indeed which u worked few years back. So I need ur kind suggestion in progressing further..
as of now i had found few architectures to implement SVPWM controller in FPGA..but the problem am facing now are:
1. In implementing FINDING SECTOR MODULE in FPGA, we need to perform iterative calculative comparisons to determine the reference sector.how do u transform that algorithmic flowchart into digital hardware implementable on FPGA?
2. secondly, how would I determine ta, tb applying those mathematical expressions using HDL or digital logic circuit synthesizable on FPGA?

as of now these are the two main questions bothering me..although i found many references speaking of CORDIC algorithm as one possible solution. but still i need to know how the complex mathematical expressions are evaluated using digital circuit?

kindly suggest me possible ways to implement & explain me in brief too..any one who help me out with this are also welcome.

anticipating ur kind response..

cheers & regards
balaji

balaji, Feb 22, 2009
11. ### balaji

Joined:
Feb 22, 2009
Messages:
2
0
Hi friend
I just started working on the same kind of project indeed which u worked few years back. So I need ur kind suggestion in progressing further..
as of now i had found few architectures to implement SVPWM controller in FPGA..but the problem am facing now are:
1. In implementing FINDING SECTOR MODULE in FPGA, we need to perform iterative calculative comparisons to determine the reference sector.how do u transform that algorithmic flowchart into digital hardware implementable on FPGA?
2. secondly, how would I determine ta, tb applying those mathematical expressions using HDL or digital logic circuit synthesizable on FPGA?

as of now these are the two main questions bothering me..although i found many references speaking of CORDIC algorithm as one possible solution. but still i need to know how the complex mathematical expressions are evaluated using digital circuit?

kindly suggest me possible ways to implement & explain me in brief too..any one who help me out with this are also welcome.

anticipating ur kind response..

cheers & regards
balaji

balaji, Feb 22, 2009
12. ### aishwarya0003

Joined:
May 17, 2009
Messages:
1
0
Hey!!
M also not able to generate the code for SVM VSI???
Can u help me out???

aishwarya0003, May 18, 2009
13. ### Colllins Nana

Joined:
Oct 29, 2015
Messages:
3
0
Hello Sir!

I ´am a Study i, in the moment I working about a project “Implementation a SVM ( SVPWM) in FPGA with VHDL”.

The PWM Program is already existing and my task is to insert the LUT and made some changes. So as I am beginner in VHDL, I would like to ask for a help. Is it possible to send me your VHDL code so I use it as reference.

TASK: - Insert in the existing Program the LUT (LOOK UP Table) dependent of space vector Diagram other states of witching.

thank u

Colllins Nana, Oct 29, 2015
14. ### Colllins Nana

Joined:
Oct 29, 2015
Messages:
3
0
THIS MY MAIN PRGRAM

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.math_real.ALL;

ENTITY I2C_modulator_tb IS

END I2C_modulator_tb;

ARCHITECTURE behavior OF I2C_modulator_tb IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Modulator
PORT(
clock : IN std_logic;
reset : IN std_logic;
scl : IN std_logic;
sda : INOUT std_logic;
phaseLFullbridge : OUT std_ulogic_vector(2 downto 0);
phaseLHalfbridge : OUT std_ulogic_vector(2 downto 0);
indicator : out std_ulogic_vector(5 downto 0);
sync_out : out std_logic;
testbit2 : OUT std_logic
-- index2 : OUT std_logic_vector(10 downto 0);
-- index1 : OUT std_logic_vector(10 downto 0)

);
END COMPONENT;

--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal scl : std_logic := '0';

--BiDirs
signal sda : std_logic;

--Outputs
signal sync_out : std_logic;
signal testbit2 : std_logic;
signal phaseLFullbridge : std_ulogic_vector(2 downto 0);
signal phaseLHalfbridge : std_ulogic_vector(2 downto 0);
signal indicator : std_ulogic_vector(5 downto 0);

-- signal index2 : std_logic_vector(10 downto 0);
-- signal index1 : std_logic_vector(10 downto 0);

-- Clock period definitions
constant clock_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: Modulator PORT MAP (
clock => clock,
reset => reset,
scl => scl,
sda => sda,
phaseLFullbridge => phaseLFullbridge,
phaseLHalfbridge => phaseLHalfbridge,
testbit2 => testbit2,
-- index2 => index2,
-- index1 => index1,
sync_out => sync_out,
indicator => indicator
);

-- Clock process definitions
clock_process rocess
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
sda <= 'H';
scl <= '0';
wait for 100ns;
reset <= '0';

-- sda <= '1';
wait for clock_period * 1000;
wait for 100 ns;

wait for clock_period*10;

-- insert stimulus here

wait;
end process;

END;

Colllins Nana, Oct 29, 2015