Synopsys Presto VHDL

[Tom Verbeure]

Hi All,

It seems that Presto VHDL does not support a number of VHDL constructs
that the previous VHDL compiler seemed to handle without problems,
especially when it comes to selecting variable slices of a vector. I've
tried to search SolvNet for a list with differences, but there doesn't
seem to be an article available.
To make things worse, the 64-bit version of DC doesn't support the
previous non-Presto compiler, so basically it seems I'm stuck and have
to rewrite a bunch of code. Sigh... :-(

I have logged a support call with Synopsys to get information for them
but if anybody here already knows more about this and could comment
about it, that would be very helpful.

Tom

 

[Wallclimber]

Update: it seems we were running into a number of Presto bugs rather
than reduced features. It's a bit scary that some fairly trivial code
constructs were not catched by Synopsys during regression testing, but
I guess that an inherent problem in the software industry. :-(

Presto seems to have dramatically improved support for a number of
VHDL features (multi-dim arrays, global static constants in port
mappings etc). I guess I'll just have to wait till it really works...

Tom