synthesis equivalent statement/code/suggestions ?

[Rama]

Hello,

I have this quesiton - on writing a synthesis equivalent code -

Question on how to write a synthesis equivalent code in VHDL for the
below code -

Counter is a synchronous with Clock and has a synchro. reset inside.

*********************************************************************************
signal CNT_OUT : unsigned ( 9 downto 0 );

begin

counter_dut : count1 ( clk => CLK,
reset => reset,
cntout => CNT_OUT );

---- this statement is what my question is about really
-- How does the synthesis engine interpret this statement.
-- is it okay to give a decimal integer value here on the right side of
the comparison ?


MISER_PLL_RESETN <= '1' when (CNT_OUT >= 50 and CNT_OUT <= 100) else

'0' ;

Appreciate any help / suggestions on this. Thanks.

Regards,
Rama

 

[mysticlol]

use to_integer() or conv_integer()

Regards,
JK

 

[Rob Dekker]

signal CNT_OUT : unsigned ( 9 downto 0 ); .....
MISER_PLL_RESETN <= '1' when (CNT_OUT >= 50 and CNT_OUT <= 100) else '0' ; ......
-- How does the synthesis engine interpret this statement.

It creates two 10-bit comparators and an AND gate.

-- is it okay to give a decimal integer value here on the right side of
the comparison ?

From a language (compilation) point of view, it depends on where you got the 'unsigned' type from.
If you are using the IEEE 'numeric_std' package (and you better!) then the answer is Yes.
It is OK, because the numeric_std package contains a definition for a >= operator (and also a <= operator) which accepts a unsigned
on the left and a natural (integer) on the right :

From the numeric_std package :

function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
..
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;

So the code should compile as-is.

Now for synthesis, you are fine too. Don't be concerned that there are going to be 32 bit comparators.
10 bit comparators is enough and synthesis tools will know that.