Timer

Discussion in 'VHDL' started by melhosseini, Jan 24, 2008.

  1. melhosseini

    melhosseini Guest

    Dear Guys,
    I need to design a timer in vhdl from 0 min:00 sec to 9min:59 sec. the
    circuit must have a start, stop and reset buttons. the output must be
    seven segment display coded. consider that a reliable 1 Hz clock
    signal is availbel

    thanks in advance
    melhosseini, Jan 24, 2008
    #1
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  2. On Thu, 24 Jan 2008 01:56:14 -0800 (PST),
    melhosseini <> wrote:

    >Dear Guys,
    >I need to design a timer in vhdl from 0 min:00 sec to 9min:59 sec. the
    >circuit must have a start, stop and reset buttons. the output must be
    >seven segment display coded. consider that a reliable 1 Hz clock
    >signal is availbel


    That's nice to hear. I very much hope that the grade you get
    reflects the quality of your work and the effort you put in.

    I wonder what will happen if the user of this device pushes
    and releases a button between ticks of the 1Hz clock?

    >thanks in advance


    You're always most welcome.
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    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

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    The contents of this message may contain personal views which
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    Jonathan Bromley, Jan 24, 2008
    #2
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