Timing probems

Discussion in 'VHDL' started by chema15, Sep 4, 2008.

  1. chema15

    chema15

    Joined:
    Jul 21, 2008
    Messages:
    2
    Hi, I designed a cordic block that has a fmax of 200 Mhz and I have a 18 bits counter that provides the angle for cordic block, this counter has a fmax of 210 Mhz. Here I don't have problems, but when I connect both the fmax is 40 Mhz and I need 150 Mhz !!!!

    Do you have an idea to improve the fmax when I connect both?
    Is it necessary to rebuild the blocks?

    Thanks..
    chema15, Sep 4, 2008
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Kieran Francisco

    Timing Diagram to HDL Translation

    Kieran Francisco, Sep 8, 2003, in forum: VHDL
    Replies:
    9
    Views:
    1,272
    VhdlCohen
    Sep 17, 2003
  2. Kload

    Strange Timing Problem

    Kload, Oct 23, 2003, in forum: VHDL
    Replies:
    2
    Views:
    572
    Kload
    Oct 23, 2003
  3. Kload
    Replies:
    1
    Views:
    541
    John_H
    Oct 23, 2003
  4. Timmy
    Replies:
    5
    Views:
    454
    cringecoder@gmail.com
    Jul 9, 2007
  5. Jimmy

    Probems with Replace Command

    Jimmy, Sep 3, 2005, in forum: ASP General
    Replies:
    2
    Views:
    98
    Jimmy
    Sep 5, 2005
Loading...

Share This Page