VCD generation, ncsim, and primepower (first-timer)

[sohaibm]

Hello Everyone,
Please can any one help me with this:
I have testbench in VHDL with synthesized netlist in VERILOG, I want to generate the VCD files using ncsim, and then figure out the activity power with Primepower,
this is the code I am using to generate the VCD files in NCSIM:
ncsim> database -open vcd.db -vcd -default -into VCD.db/dump.vcd
ncsim> probe -create -vcd testbench -database vcd.db -all -variables -depth all
the VCD file is generated, when i simulate with primepower i am getting the warning where most of the nets are not covered by the VCD file saying: Please check $dumpvars in Verilog testbench to make sure all nets are dumpped.
Although the testbench is in vhdl should i still put the $dumpvars in the verilog netlist i am trying to simulate? if yes what is the code that should be in the verilog netlist? If no, what is the exact procedure in case of vhdl testbench with verilog netlist?
I appreciate any help,
Thank you
Sohaib

 

[sohaibm]

ncsim again

Hello again,
here is the story:
it turned out that because i ran the unsynthesized vhdl first, the ncsim is still using the old lib from the worklib. So that is explains part of the problem
when i deleted the old lib i am getting some wired errors while simulating

ncvhdl: 05.10-p004: (c) Copyright 1995-2003 Cadence Design Systems, Inc.
ncvlog: 05.10-p004: (c) Copyright 1995-2003 Cadence Design Systems, Inc.
ncvhdl: 05.10-p004: (c) Copyright 1995-2003 Cadence Design Systems, Inc.
ncelab: 05.10-p004: (c) Copyright 1995-2003 Cadence Design Systems, Inc.
ncelab: *E,CUCPNA: component port RCELL.FB_IN not associated with any formal [5.2.1.2].
ncelab: *E,CUCPNA: component port RCELL.V_RCS not associated with any formal [5.2.1.2].
ncelab: *E,CUCPNA: component port RCELL.H_RCS not associated with any formal [5.2.1.2].
ncelab: *E,CUCPNA: component port RCELL.DGL_RCS not associated with any formal [5.2.1.2].
ncelab: *E,CUCPNA: component port RCELL.CR_RC not associated with any formal [5.2.1.2].
ncelab: *E,CUCPNA: component port RCELL.HEL_IN not associated with any formal [5.2.1.2].
ncelab: *E,CUCPNA: component port RCELL.VEL_IN not associated with any formal [5.2.1.2].
ncelab: *E,CUCPNA: component port RCELL.CONTEXT not associated with any formal [5.2.1.2].
ncelab: *E,CUCPNA: component port RCELL.FB_OUT not associated with any formal [5.2.1.2].
ncelab: *E,CUCPNA: component port RCELL.HEL_OUT not associated with any formal [5.2.1.2].
ncelab: *E,CUCPNA: component port RCELL.VEL_OUT not associated with any formal [5.2.1.2].
ncelab: *E,CUCPNA: component port RCELL.RC_OUT not associated with any formal [5.2.1.2].
module RCell ( \FB_in[23] , \FB_in[22] , \FB_in[21] , \FB_in[20] , \FB_in[19] ,
|
ncelab: *E,CFEPLM (/ubc/ece/home/soc/grads/sohaibm/work/RCwork/synopsys/project1/RCell.v,18942|11): Foreign module port FB_in[23] of mode in must be associated with port/signal of entity/component RCELL (../testbench/RCTestBench.vhd: line 15, position 15).
module RCell ( \FB_in[23] , \FB_in[22] , \FB_in[21] , \FB_in[20] , \FB_in[19] ,
|
ncelab: *E,CFEPLM (/ubc/ece/home/soc/grads/sohaibm/work/RCwork/synopsys/project1/RCell.v,18942|11): Foreign module port FB_in[22] of mode in must be associated with port/signal of entity/component RCELL (../testbench/RCTestBench.vhd: line 15, position 15).
module RCell ( \FB_in[23] , \FB_in[22] , \FB_in[21] , \FB_in[20] , \FB_in[19] ,
|
ncelab: *E,CFEPLM (/ubc/ece/home/soc/grads/sohaibm/work/RCwork/synopsys/project1/RCell.v,18942|11): Foreign module port FB_in[21] of mode in must be associated with port/signal of entity/component RCELL (../testbench/RCTestBench.vhd: line 15, position 15).
module RCell ( \FB_in[23] , \FB_in[22] , \FB_in[21] , \FB_in[20] , \FB_in[19] ,
|
ncelab: *E,CFEPLM (/ubc/ece/home/soc/grads/sohaibm/work/RCwork/synopsys/project1/RCell.v,18942|11): Foreign module port FB_in[20] of mode in must be associated with port/signal of entity/component RCELL (../testbench/RCTestBench.vhd: line 15, position 15).
module RCell ( \FB_in[23] , \FB_in[22] , \FB_in[21] , \FB_in[20] , \FB_in[19] ,
|
etc...
It seems to me that the buses are defined bit by bit in the synthesized netlist, however in the testbench i am assigning the whole bus to it:
Netlist:
module RCell ( \FB_in[23] , \FB_in[22] , \FB_in[21] , \FB_in[20] , \FB_in[19] ,
\FB_in[18] , \FB_in[17] , \FB_in[16] , \FB_in[15] , \FB_in[14] ,
\FB_in[13] , \FB_in[12] , \FB_in[11] , \FB_in[10] , \FB_in[9] , \FB_in[8] ,
\FB_in[7] , \FB_in[6] , \FB_in[5] , \FB_in[4] , \FB_in[3] , \FB_in[2] ,
\FB_in[1] , \FB_in[0] , \V_RCs[111] , \V_RCs[110] , \V_RCs[109] ,
\V_RCs[108] , \V_RCs[107] , \V_RCs[106] , \V_RCs[105] , \V_RCs[104] ,
\V_RCs[103] , \V_RCs[102] , \V_RCs[101] , \V_RCs[100] , \V_RCs[99] ,
\V_RCs[98] , \V_RCs[97] , \V_RCs[96] , \V_RCs[95] , \V_RCs[94] ,
\V_RCs[93] , \V_RCs[92] , \V_RCs[91] , \V_RCs[90] , \V_RCs[89] ,
Testbench:
RCell_unit: RCell PORT MAP(
FB_in => s_FB_in,
V_RCs => s_V_RCs,
H_RCs => s_H_RCs,
Dgl_RCs => s_Dgl_RCs,
CR_RC => s_CR_RC,
HEL_in => s_HEL_in,
VEL_in => s_VEL_in,
context => s_context,
cntrl_bf => s_cntrl_bf,
clock => s_clock,
--testing_port => s_--testing_port,
FB_out => s_FB_out,
HEL_out => s_HEL_out,
VEL_out => s_VEL_out,
RC_out => s_RC_out
);

Please anyone can help me understand how can I solve this mismatch between the netlist and the testbench?
thanks for any comment or help,
Sohaib