Verilog Implementation of FIR Filter

Discussion in 'VHDL' started by Rahul Iyer, Feb 19, 2008.

  1. Rahul Iyer

    Rahul Iyer Guest

    HI,
    I want the verilog implementation of N-Tap FIR filter.... I am bit in
    a fix, to use a Distributed arithmetic or MAC unit... I suppose if I
    am using Vertex 4 FPGA's that have inbuilt Multiplier, then I dont
    need DA or MAC unit??
    Kindly suggest...

    Regards
    Rahul
     
    Rahul Iyer, Feb 19, 2008
    #1
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  2. Rahul Iyer

    gally Guest

    On Feb 19, 5:34 pm, Rahul Iyer <> wrote:
    > HI,
    > I want the verilog implementation of N-Tap FIR filter.... I am bit in
    > a fix, to use a Distributed arithmetic or MAC unit... I suppose if I
    > am using Vertex 4 FPGA's that have inbuilt Multiplier, then I dont
    > need DA or MAC unit??
    > Kindly suggest...
    >
    > Regards
    > Rahul


    I think u can design by usin Matlab. There u can find a system
    generate option in edatool design. You can design whichever filter u
    want, and in which language u want, u can
     
    gally, Feb 20, 2008
    #2
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