Verilog Question

Discussion in 'VHDL' started by Ann, Dec 27, 2007.

  1. Ann

    Ann Guest

    Could you please explain what the following code does

    // HOST Memory Array (written via serial interface)
    reg [(REGWIDTH-1):0] HOSTmemory[(REGDEPTH-1):0];

    // FPGA Memory Array (written directly by FPGA)
    reg [(REGWIDTH-1):0] FPGAmemory[(REGDEPTH-1):0];
    //
    ======================================================================
    // Fetch READ value
    assign memRD = (memRA[7] == HI)?
    FPGAmemory[memRA[(REGLOG2DEPTH-1):0]]:
    HOSTmemory[memRA[(REGLOG2DEPTH-1):0]];
    //
    ======================================================================
    // HOST Register Write Process
    always @ (posedge clk)
    begin
    if ((memWS == HI) && (memWA[(REGWIDTH-1):REGLOG2DEPTH] == 0) )
    HOSTmemory[memWA[(REGLOG2DEPTH-1):0]] <= memWD;
    else
    HOSTmemory[memWA[(REGLOG2DEPTH-1):0]] <=
    HOSTmemory[memWA[(REGLOG2DEPTH-1):0]];
    end


    I dont understand the "Fetch Read Value" and the "HOST Register Write
    Process".
     
    Ann, Dec 27, 2007
    #1
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  2. Ann

    Guest

    This group is for VHDL. Verilog is a different language.

    Try comp.lang.verilog.
     
    , Dec 27, 2007
    #2
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  3. On Thu, 27 Dec 2007 09:19:22 -0800 (PST),
    Ann <> wrote:

    >Could you please explain what the following code does

    [...]
    >I dont understand the "Fetch Read Value" and the
    > "HOST Register Write Process".


    As Mike Shepherd said, it's Verilog so it will attract
    better answers on comp.lang.verilog - but some of us
    inhabit both, so here goes.

    First, what part of it don't you understand? It looks
    like pretty standard Verilog to me.

    Secondly, the original author has gotten pretty confused
    about parameterization and a few other things. In
    particular:

    (1) Why, in the middle of code that otherwise has been
    carefully parameterized, do we find this condition as
    the memory space selector?

    (memRA[7] == HI)?

    Maybe the number 7 has mystical significance in some
    cultures; in mine, it doesn't. Give it a name.

    (2) The write process is enabled by some complicated
    condition; if that condition is false, we execute the
    following code...

    > else
    > HOSTmemory[memWA[(REGLOG2DEPTH-1):0]] <=
    > HOSTmemory[memWA[(REGLOG2DEPTH-1):0]];


    Eh? Why is it *ever* a good idea to write "A <= A" ?

    (3) Comments. The comments claim ...

    >// HOST Memory Array (written via serial interface)


    but it's fibbing, isn't it? Unless "memWD" is derived
    from the serial interface somehow.

    ~~~~~~~~~~~~~

    So, in summary:
    a) take it to comp.lang.verilog;
    b) be clearer about what you don't understand, please;
    c) go back to the author and sanity-check the questions
    I posed above.

    thanks
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Dec 28, 2007
    #3
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