Verilog Task Call with VHDL TestBench

Discussion in 'VHDL' started by masini, Apr 5, 2006.

  1. masini

    masini Guest

    Hello,

    anyone know how I could call a verilog task through a VHDL Testbench?
    I have a protected Verilog modul with an VHDL interface. I have built a
    Tesbench in VHDL. But now I need also to call the task in the protected
    Verilog.
    I think in Verilog Testbench would do it so:
    <instance_name>.task_name;

    And in VHDL???

    Thank you very much.

    Masini
     
    masini, Apr 5, 2006
    #1
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