Common Testbench for both VHDL/Verilog designs

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Hello friends,

I am looking for advice on how to deal with this issue.

I have a common testbench that I use to simulate my RTL (VHDL) and gate netlists (Verilog).

I have a state machine encoded using enumerated variables in my VHDL RTL. I am using NC_mirror to get the state machine into my testbench for various diagnostic checks. In my RTL simulation, I compare the state to its enumerated value. The problem occurs in my gate simulation because I can no longer use enumerated values.

For example,

type act_state is (idle, STATE1, STATE2, STATE3, STATE4);
state : act_state;

ASIC_SM_RTL : act_state;
nc_mirror (DUT:statem:state, :ASIC_SM_RTL);

if ASIC_SM_RTL /= STATE2 then
assert ----

This works fine for RTL.

For my gate netlist, I do the following:

ASIC_SM_GATE: std_logic_vector(3 downto 0);
nc_mirror (DUT: statem:state, :ASIC_SM_GATE);

if state_to_string(ASIC_SM_GATE) /= "STATE2" then
assert ----

where state_to_string is a function that takes the state as a standard logic vector and returns a string.

Now this is a problem because I have to maintain two separate testbenches for RTL and Gate simulations.

Is there a better way to do this? I know that we do not have compiler directives in NC-VHDL which will allow me to do two different things in the same testbench file based on what I am simulating.

Your suggestions are much appreciated.
 

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