Vernier Interpolation

[LearnVHDL]

Dear All,
I'm working on a project about time interval counter using vernier interpolation principle to get a higher resolution. If you are not family with vernier interpolation, it's totally fine, coz my question is quite general.

Here's my problem:
Input: Clk_ref with 100MHz
Input: Start_trigger
Output: Clk1 with 100MHz * (16/17) when the Start trigger signal goes high

I'm using virtex 4, I can easily get the output frequency with the DCM in FPGA. This is what I did. I fed the input clk_ref to the DCM and then I would get the output with the frequency that I want.

However, I don't want the output freq to be generated right away. I want it to happen AT THE MOMENT Start_trigger signal goes high.

Feeding the Clk1 and Start_trigger into an AND gate isn't an solution. Because the output of the AND gate will not go high at the moment(with some delay) Start_trigger go high. The output of the AND will just wait till Clk1 goes high.


This is what i want:
Clk_ref:xxxxxxxxxx|____|-----|____|-----|____|-----|____|-----|____|
Start_trigger:xxxxxx_________________|------------------------------------
Clk1:xxxxxxxxxxxxxx__________________|-------|_____|------|_____|------

Summary:
* freq of Clk1 = freq of Clk_ref * (16/17) <--- I can do this with DCM
* Clk1 will be triggered by Start_trigger;

Thanks in advance. Any suggestion and idea will be appreciated!!! Thanks.

 

[quantum_dot]

You can use gated clock option. Stanadard primitives are available in Viterx-4 to support gated clock. :driver:

 

[LearnVHDL]

quantom_dot?

"You can use gated clock option. Stanadard primitives are available in Viterx-4 to support gated clock..."

gated clock?? please provide more detail... Thanks..

 

[quantum_dot]

you can use BUFGCE primitive available in Virtex devices. This is a global clock buffer with a single gated input. When Clk Enable is high, the input is transferred to output.

Here is the VHDL instantiation template for this primitive

component BUFGCE
port (O : out STD_ULOGIC;
CE : in STD_ULOGIC;
I : in STD_ULOGIC);
end component;

BUFGCE_INSTANCE_NAME : BUFGCE
port map (O => user_O,
CE => user_CE,
I => user_I);

 

[LearnVHDL]

"If the CE input is Low prior to the incoming rising clock edge, the following clock pulse does not pass through the clock buffer, and the output stays Low. Any level change of CE during the incoming clock High pulse has no effect until the clock transitions Low. The output stays Low when the clock is disabled. However, when the clock is being disabled it completes the clock High pulse." from Virtex User Guide...

Thanks Quantum. It's not working like what I wanted. But Thanks tho. Any other idea??

 

[quantum_dot]

one more idea... May be you can synchronize your start trigger pulse with incoming clock and then use the gated clock pulse. This way you will always have the output clock starting just at the moment start trigger is asserted.
:driver:

 

[LearnVHDL]

"May be you can synchronize your start trigger pulse with incoming clock and then use the gated clock pulse."

How can I synchronize my start trigger pulse with incoming clk?? Thanks Quantum.

 

[quantum_dot]

You can use this simple logic.


signal Sync_trigger : std_logic ; -- sync trigger pulse

process(Clk_ref, rst) -- rst is system reset signal
begin

if Clk_ref'event and Clk_ref = '1' then
if reset = '1' then
Sync_trigger <= '0';
else
Sync_trigger <= Start_trigger;
end if;
end if;

end process;

Sync_trigger is will go high only on the rising edge of clk_ref. and then you can use this synchronised pulse to get your output clock. Hope this will help you....
:driver: