Vernier Interpolation

Discussion in 'VHDL' started by LearnVHDL, Mar 18, 2007.

  1. LearnVHDL

    LearnVHDL

    Joined:
    Mar 8, 2007
    Messages:
    6
    Dear All,
    I'm working on a project about time interval counter using vernier interpolation principle to get a higher resolution. If you are not family with vernier interpolation, it's totally fine, coz my question is quite general.

    Here's my problem:
    Input: Clk_ref with 100MHz
    Input: Start_trigger
    Output: Clk1 with 100MHz * (16/17) when the Start trigger signal goes high

    I'm using virtex 4, I can easily get the output frequency with the DCM in FPGA. This is what I did. I fed the input clk_ref to the DCM and then I would get the output with the frequency that I want.

    However, I don't want the output freq to be generated right away. I want it to happen AT THE MOMENT Start_trigger signal goes high.

    Feeding the Clk1 and Start_trigger into an AND gate isn't an solution. Because the output of the AND gate will not go high at the moment(with some delay) Start_trigger go high. The output of the AND will just wait till Clk1 goes high.


    This is what i want:
    Clk_ref:xxxxxxxxxx|____|-----|____|-----|____|-----|____|-----|____|
    Start_trigger:xxxxxx_________________|------------------------------------
    Clk1:xxxxxxxxxxxxxx__________________|-------|_____|------|_____|------

    Summary:
    * freq of Clk1 = freq of Clk_ref * (16/17) <--- I can do this with DCM
    * Clk1 will be triggered by Start_trigger;

    Thanks in advance. Any suggestion and idea will be appreciated!!! Thanks.
     
    LearnVHDL, Mar 18, 2007
    #1
    1. Advertising

  2. LearnVHDL

    quantum_dot

    Joined:
    Nov 21, 2006
    Messages:
    31
    You can use gated clock option. Stanadard primitives are available in Viterx-4 to support gated clock. :driver:
     
    quantum_dot, Mar 19, 2007
    #2
    1. Advertising

  3. LearnVHDL

    LearnVHDL

    Joined:
    Mar 8, 2007
    Messages:
    6
    quantom_dot?

    "You can use gated clock option. Stanadard primitives are available in Viterx-4 to support gated clock..."

    gated clock?? please provide more detail... Thanks..
     
    LearnVHDL, Mar 19, 2007
    #3
  4. LearnVHDL

    quantum_dot

    Joined:
    Nov 21, 2006
    Messages:
    31
    you can use BUFGCE primitive available in Virtex devices. This is a global clock buffer with a single gated input. When Clk Enable is high, the input is transferred to output.

    Here is the VHDL instantiation template for this primitive

    component BUFGCE
    port (O : out STD_ULOGIC;
    CE : in STD_ULOGIC;
    I : in STD_ULOGIC);
    end component;

    BUFGCE_INSTANCE_NAME : BUFGCE
    port map (O => user_O,
    CE => user_CE,
    I => user_I);
     
    quantum_dot, Mar 20, 2007
    #4
  5. LearnVHDL

    LearnVHDL

    Joined:
    Mar 8, 2007
    Messages:
    6
    "If the CE input is Low prior to the incoming rising clock edge, the following clock pulse does not pass through the clock buffer, and the output stays Low. Any level change of CE during the incoming clock High pulse has no effect until the clock transitions Low. The output stays Low when the clock is disabled. However, when the clock is being disabled it completes the clock High pulse." from Virtex User Guide...

    Thanks Quantum. It's not working like what I wanted. But Thanks tho. Any other idea??
     
    LearnVHDL, Mar 20, 2007
    #5
  6. LearnVHDL

    quantum_dot

    Joined:
    Nov 21, 2006
    Messages:
    31
    one more idea... May be you can synchronize your start trigger pulse with incoming clock and then use the gated clock pulse. This way you will always have the output clock starting just at the moment start trigger is asserted.
    :driver:
     
    quantum_dot, Mar 21, 2007
    #6
  7. LearnVHDL

    LearnVHDL

    Joined:
    Mar 8, 2007
    Messages:
    6
    "May be you can synchronize your start trigger pulse with incoming clock and then use the gated clock pulse."

    How can I synchronize my start trigger pulse with incoming clk?? Thanks Quantum.
     
    LearnVHDL, Mar 21, 2007
    #7
  8. LearnVHDL

    quantum_dot

    Joined:
    Nov 21, 2006
    Messages:
    31
    You can use this simple logic.


    signal Sync_trigger : std_logic ; -- sync trigger pulse

    process(Clk_ref, rst) -- rst is system reset signal
    begin

    if Clk_ref'event and Clk_ref = '1' then
    if reset = '1' then
    Sync_trigger <= '0';
    else
    Sync_trigger <= Start_trigger;
    end if;
    end if;

    end process;

    Sync_trigger is will go high only on the rising edge of clk_ref. and then you can use this synchronised pulse to get your output clock. Hope this will help you....
    :driver:
     
    quantum_dot, Mar 23, 2007
    #8
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. df84077@gmail.com

    Linear interpolation in vhdl

    df84077@gmail.com, Aug 21, 2005, in forum: VHDL
    Replies:
    8
    Views:
    6,027
    Researcher_123
    Oct 7, 2011
  2. Mat W
    Replies:
    3
    Views:
    434
    Skeleton Man
    May 21, 2004
  3. \Rob\
    Replies:
    8
    Views:
    653
    Daniel Kirsch
    Feb 24, 2006
  4. Michele Puccini
    Replies:
    0
    Views:
    409
    Michele Puccini
    Nov 9, 2003
  5. Raj
    Replies:
    2
    Views:
    1,910
Loading...

Share This Page