VHDL-200X Fixed Point Divider

Discussion in 'VHDL' started by Divyang M, Aug 18, 2005.

  1. Divyang M

    Divyang M Guest

    Hi,

    I was wondering if the VHDL-200X fixed point divider is synthesizable
    (by Altera Quartus)?

    If so, what is the expected performance (speed / area) and is it
    possible to pipeline the function for greater speed?

    Thanks,
    Divyang M
     
    Divyang M, Aug 18, 2005
    #1
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  2. Divyang M

    David Bishop Guest

    Divyang M wrote:
    > Hi,
    >
    > I was wondering if the VHDL-200X fixed point divider is synthesizable
    > (by Altera Quartus)?
    >
    > If so, what is the expected performance (speed / area) and is it
    > possible to pipeline the function for greater speed?


    It depends. The fixed point divide uses a signed divide from
    numeric_std. It works in Synplicity, but I don't know about quartus.

    I just finished a Newton Raphson divide routine for fixed point that I
    will post soon. That one takes about 8 multiplies.
     
    David Bishop, Aug 19, 2005
    #2
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  3. Divyang M

    Divyang M Guest

    Thanks David. I will look forward to the divide routine.

    I still owe you the part of the code using the fixed_pkg that works
    with Quartus 4.2 but not with Quartus 5.0 (from one of my earlier
    posts). I will e-mail it as soon as I pack it into a user-friendly
    fashion.

    --Divyang M.
     
    Divyang M, Aug 19, 2005
    #3
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