VHDL and extracing equations

Discussion in 'VHDL' started by buke2, Jul 28, 2004.

  1. buke2

    buke2 Guest

    Hello all,
    anybody knows how can I extract equations from Xilinx schematic?
    I tried in Schematic Editor: Option->ExportNetlist and VHD file has been
    generated...but to get clear equations (Out=f(In)) I must translate whole of
    file...

    Maybe somhere is tool for extracting euations from VHDL file?

    Regards
    Kuba
    buke2, Jul 28, 2004
    #1
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  2. Hi Kuba,

    buke2 wrote:

    >Hello all,
    >anybody knows how can I extract equations from Xilinx schematic?
    >I tried in Schematic Editor: Option->ExportNetlist and VHD file has been
    >generated...but to get clear equations (Out=f(In)) I must translate whole of
    >file...
    >
    >

    Do you need them into vhdl ? Otherwise you can perhaps use edif2blif to
    generate a blif file.

    >Maybe somhere is tool for extracting euations from VHDL file?
    >
    >

    The official level of input is a transistor netlist, but you can look
    for TLL product from TransEDA/TNI-Valiosys
    Perhaps do you have a way to keep your netlist as input.

    TLL can make you a VHDL or a Verilog file with sequential process and
    combinatory process.

    Then you have your equations.

    >Regards
    >Kuba
    >
    >
    >
    >
    >

    Regards,
    JaI
    Just an Illusion, Jul 28, 2004
    #2
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  3. buke2

    buke2 Guest

    "Just an Illusion" <> wrote in message
    news:...
    > Hi Kuba,
    >
    > buke2 wrote:
    >
    > >Hello all,
    > >anybody knows how can I extract equations from Xilinx schematic?
    > >I tried in Schematic Editor: Option->ExportNetlist and VHD file has been
    > >generated...but to get clear equations (Out=f(In)) I must translate whole

    of
    > >file...
    > >
    > >

    > Do you need them into vhdl ? Otherwise you can perhaps use edif2blif to
    > generate a blif file.
    >
    > >Maybe somhere is tool for extracting euations from VHDL file?
    > >
    > >

    > The official level of input is a transistor netlist, but you can look
    > for TLL product from TransEDA/TNI-Valiosys
    > Perhaps do you have a way to keep your netlist as input.
    >
    > TLL can make you a VHDL or a Verilog file with sequential process and
    > combinatory process.
    >
    > Then you have your equations.


    THX!!!!!!
    buke2, Jul 28, 2004
    #3
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