VHDL code to schematic generator

Discussion in 'VHDL' started by pigeglad, Nov 5, 2003.

  1. pigeglad

    pigeglad Guest

    Hello group



    I'm reviewing a design with more than 170 VHDL files (2.4 MB), and I could
    strongly benefit from a tool that can generate a schematic based on the VHDL
    files.



    Is there a program that can help me and can you perhaps recommend one?



    Thanks in advanced



    Jan
     
    pigeglad, Nov 5, 2003
    #1
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  2. pigeglad wrote:

    > I'm reviewing a design with more than 170 VHDL files (2.4 MB), and I could
    > strongly benefit from a tool that can generate a schematic based on the VHDL
    > files.


    Consider reviewing the simulation testbench first.
    That will tell you more about the design than
    a graphic with hundreds of boxes and thousands
    of wires.

    If you have modelsim, take a look at
    View, Dataflow once you have some waveforms up.

    You can drag in a wave and get an extendable schematic view
    of the processes in the neighborhood. You can even
    watch the data values change as you move the
    waveform cursor.

    -- Mike Treseler
     
    Mike Treseler, Nov 5, 2003
    #2
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  3. Mentor Graphics' "Renoir" can do this (although the drawings are
    pretty ugly, imho). I think Renoir is now called "HDL Designer".

    "pigeglad" <> wrote:

    :Hello group
    :
    :
    :
    :I'm reviewing a design with more than 170 VHDL files (2.4 MB), and I could
    :strongly benefit from a tool that can generate a schematic based on the VHDL
    :files.
    :
    :
    :
    :Is there a program that can help me and can you perhaps recommend one?
    :
    :
    :
    :Thanks in advanced
    :
    :
    :
    :Jan
    :
    :
     
    David R Brooks, Nov 5, 2003
    #3
  4. pigeglad

    VhdlCohen Guest

    Since you guys are listing the possible tools, let me throw in
    Cadence NC-Sim
    @HDL @designer www.athdl.com
    Novas tools

    ----------------------------------------------------------------------------
    Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
    http://www.vhdlcohen.com/
    Author of following textbooks:
    * Using PSL/SUGAR with Verilog and VHDL
    Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
    * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
    0-9705394-2-8
    * Component Design by Example ", 2001 isbn 0-9705394-0-1
    * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
    * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
    ------------------------------------------------------------------------------
     
    VhdlCohen, Nov 6, 2003
    #4
  5. pigeglad

    gary Guest

    And Aldec's Active-HDL www.aldec.com


    "pigeglad" <> wrote in message
    news:3fa9628d$0$27457$...
    > Hello group
    >
    >
    >
    > I'm reviewing a design with more than 170 VHDL files (2.4 MB), and I could
    > strongly benefit from a tool that can generate a schematic based on the

    VHDL
    > files.
    >
    >
    >
    > Is there a program that can help me and can you perhaps recommend one?
    >
    >
    >
    > Thanks in advanced
    >
    >
    >
    > Jan
    >
    >
    >
     
    gary, Nov 9, 2003
    #5
  6. pigeglad

    Alan Fitch Guest

    "pigeglad" <> wrote in message
    news:3fa9628d$0$27457$...
    > Hello group
    >
    >
    >
    > I'm reviewing a design with more than 170 VHDL files (2.4 MB), and I

    could
    > strongly benefit from a tool that can generate a schematic based on

    the VHDL
    > files.
    >
    >
    >
    > Is there a program that can help me and can you perhaps recommend

    one?
    >


    I can't recommend one, but I have heard of a tool called
    "HDL Companion" recently, which claims to do what you describe.

    Also I think Mentor's HDL Designer can do that.

    regards

    Alan



    --
    Alan Fitch
    Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
    Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
    1AW, UK
    Tel: +44 (0)1425 471223 mail:

    Fax: +44 (0)1425 471573 Web:
    http://www.doulos.com

    The contents of this message may contain personal views which are not
    the
    views of Doulos Ltd., unless specifically stated.
     
    Alan Fitch, Nov 10, 2003
    #6
  7. "pigeglad" <> schreef in bericht
    news:3fa9628d$0$27457$...
    > Hello group
    >
    >
    >
    > I'm reviewing a design with more than 170 VHDL files (2.4 MB), and I could
    > strongly benefit from a tool that can generate a schematic based on the

    VHDL
    > files.
    >
    >
    >
    > Is there a program that can help me and can you perhaps recommend one?
    >
    >
    >
    > Thanks in advanced
    >
    >
    >
    > Jan
    >
    >
    >

    Try the Xilinx ISE webpack. I think this feature is included (it's in the
    commercial verion, i'm not sure about the Webpack)

    Mark
     
    Mark van de Belt, Nov 20, 2003
    #7
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